Right, Danny, that's what I meant, the built in tools are limited, need to bring in test instruments for some diagnostics. DCA has always done fine with its pattern trigger and the addition of triggering on bit sequences is great... when will you have a new, high sampling rate mainframe? Or did I miss that release?
When I say that "only errors count" what I mean is that the BER is the ultimate judge of performance. If the BER is acceptable, move along. When it's not, then get to work. Certainly including analaysis of clock recovery performance/response!
Built in tools have the advantage of grabbing the signal without introducing cables, connectors and all the systematics associated with them, but are usually limited in flexibility, for example, ability to use non PRBS test patterns
There's so much more to the "only errors count" related to jitter if you care about the quality of the recovered clock... if you are designing/testing a CDR or a SERDES architecture - then you need to consider the spectral contents of jitter, esp. low frequency ones - which are extremely hard to be measured propperly...
Thanks Ransom for this lecture. Nowadays we started to use OMA (optical modulation amplitude) because what matters is not the level on a logic 1 or 0, but the ability of a receiver to distinguish a 1 from 0. What do you think about this approach?
Over the last decade the scope jitter analysis software has come a long way. We get mostly consistent answers from different vendors, which is comforting. How accurate do you think your jitter measurements are?
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Blog Doing Math in FPGAs Tom Burke 16 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...