Clearly at the leading edge, MLC NAND flash requires extensive ECC and also a controller that will keep moving data on so that all the memory cells get similar wear....as they can only do a limited number of read/write cycles and ECC to correct for altered bits adds to the wear.
One implication of this "wear leveling" is that at the extreme the effective capacity of a leading-edge NAND flash memory reduces over time.
I am not sure whether the manufacturers provide additional capacity so that the memory "wears down" toward the advertized capacity ...or they produce what they produce and reckon it is down to the controller to "manage" the situation.
Blog Doing Math in FPGAs Tom Burke 23 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...