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100% agreee
Jslee0   9/12/2013 12:31:21 PM
Something needs to be done. otherwise the fundamental of the SV will be hit a bubble burst.

Max The Magnificent
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I'm not an expert, but...
Max The Magnificent   9/12/2013 4:07:11 PM
I'm not an expert (and I don't even play one on TV), but this all seems to make a lot of sense to me.

Matthieu Wipliez
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Couldn't agree more
Matthieu Wipliez   9/13/2013 4:21:36 AM
Especially as I am the co-founder of an EDA start-up company :-) At Synflow we are reaching out to semiconductor companies to find our first client/strategic partner. This company will be the first to experiment with our product Synflow Studio, and they will have the opportunity to give us important feedback and help us improve our product, before others start using it. Take a look at our blog and our YouTube channel to learn more!

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High risk and bad exits
adapteva   9/13/2013 8:15:33 AM

Great article and a wonderful effort. Can you point to any success stories to date? I heard rumours of an option/call setup like this being used by one of the few startups that have been able to raise significant amount of funds, but of course I don't have the details..

Based on my own painful 5 year fund raising journey, there have been two challenges that have stood out.

1.) High Risk: Most VCs I have interacted with believe it's going to cost >$20M at minimum to get to an exit and there is a real risk that it will cost upwards of $100M (based on historical data points). I have been standing on my soap box for years shouting that these numbers are inflated, but it's an uphill battle. My point is that thanks to IP availability, EDA tools, and the general "virtual startup" trend it's cheaper than ever to design chips. Adapteva created four silicon tapeouts for less than $2.5M.  The risk equation changes completely if the funds needed to exit is less than $10M.

2.) Bad exits. It pains me to say that many semiconductor companies Hah I said it.:-) Maybe conservative is a better word. If only there there would be a few bubble exits like the $4.7B Chromatis exit to Lucent back in 2000. Things would get better in a hurry! There have been a few decent exits recently, like the $500M sale of Anobit to Apple, but in general exit valuations have been pretty low. System-On-Chips are the tails that wag the dogs. A key chip technology can actually move the needle by billions of dollars for large system companies. Samsung, Apple, Huawei, and Orcale are examples of companies that "get it". 

Look forward to your feedback on these two issue.


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Re: High risk and bad exits
ACOrrantia   9/13/2013 4:45:19 PM
Hello Andreas, 

Thanks for the comments. 

I was recently on a panel at the GSA Entrereneur Conference.  Tallwood Ventures and Intel Capital had a number of examples of deals they had funded with a Call Option for Intel.  Given that we technically opened our doors in April and our accelerator is currently under construction, we are far too new for exit success stories.

We have had discussions with well-known, Sand Hill Rd VCs.  Overwhelmingly, they like our model and many have committed to participating in a Series A for our accelerator graduates.  While the returns aren't as high as the traditional VC model, our deals are largely de-risked.  Before committing any money, the VC knows what the minumum return is going to be for a particular startup.  Moreover, the velocity of their capital is increases dramatically.  Instead of a typical fabless semiconductor time-to-money horizon of 8 to 10 years, our startups exit to the strategic partner in 1 to 2 years.  

The flip-side, of course, is that there is also a cap on the returns with the call option.  Realistically speaking, there aren't many startups that will return the 10X cash-on-cash that we saw in the late 90's.  So a cap isn't much of a deterent.  That said, a 3X to 4X return in 3 to 4 years is hard to pass up.  

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Re: High risk and bad exits
adapteva   9/13/2013 6:40:22 PM
Thanks for reply!

The quick exit strategy approach is certainly a good approach. It short circuits the worst part of being a semiconductor startup: waiting until the market materializes or until your customers are successful in selling to the end market. Bigger companies have deeper pockers and are much better positioned to play the long game.

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Re: High risk and bad exits
ACOrrantia   9/13/2013 7:45:55 PM
A fast exit solves many problems for investors and entrepreneurs alike.  Another advantage of this kind of model is that the strategic partner is involved very early in the development of the company and its product.  This provides the startup with laser beam focused targets with regard to market segment and technical requirements.  Therefore, the startup is not distracted or over-building a product and is able to exit that much quicker. 

User Rank
Absolutely correct
WarrenSavage   9/13/2013 7:58:21 PM
I heartily agree with many of the comments here and applaud the work of the GSA in trying to stimulate a conversation in the global semiconductor community about this topic.  I am proud to be part the Cap Lite Working Group there that worked with a great group of people who invested lots of time and effort in assembling a large coalition of companies that are genuinely interested in helping technologists get new ventures off the ground.  You might want to check out the Cap Lite Resource portal to get a sense of the companies that are part of that effort.  You might even want to check out a local Silicon Valley TV program (Press Here) that  ran a story on this awhile back called Show Me The Silicon.

I think Angel and the SKTA Innopartners team are just the start of a wave of incubators that  are part of an overall pivot in the semiconductor industry away from the VC-community.  There will be much more reliance on industry partnerships, spin-outs, etc., that will enable new ideas to get the oxygen they need to grow.  You might also be interested to check out Angel in an interview segment we did together earlier this summer on this topic.

In the end the importance of having new semiconductor companies forming is important not only for the semiconductor industry, but for the health of the entire supply chain.  While the industry has its naysayers, I feel that there is still so much innovation that has yet to come that Silicon Valley is far away from becoming the next Detroit.

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VC community been away from semiconductor industry?
Edward.Thornton   9/13/2013 8:35:53 PM

Famed EDA Industry analyst Gary Smith emalied his thoughts to me for posting here:


Although I agree with the idea of having a sponsor for a start-up I don't

think they should be assigned.  Most start-ups should have knowledgeable

leaders that know that from the beginning.  They are the ones that know

enough about their product that they can pick out an appropriate sponsor.


As for the Capital-Lite Semiconductor model, it sounds like the VC community

have been away from the Semiconductor market so long they haven't been

keeping up with all of the changes.  The should check out "We are tripping over our own

Semantics" and


they-myth-of-the-170-million-dollar-design/  .


That or GSA should give an education program for VC's interesting financing

Semiconductor Start-ups.


User Rank
Re: VC community been away from semiconductor industry?
ACOrrantia   9/16/2013 12:42:14 PM
Hello Gary,


Thanks for your thoughts.


I just wanted to clear one thing up.  We don't assign a Strategic Partner to a startup.  It's a collaborative process.  For the relationship to work, the entrepreneurs and the Strategic Partner have to have close alignment and be of like minds.  What we do is help the entrepreneurs identify Strategic Partners that might make a good potential matech.  Ultimately, however, the entrepreneurs themselves have to decide which Strategic Partner is the best fit for their startup.  Similarly for the Strategic Partners.  They too must determine the startup that is most aligned with their future needs.

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michigan0 Sang Kim First, 28nm bulk is in volume manufacturing for several years by the major semiconductor companies but not 28nm FDSOI today yet. Why not? Simply because unlike 28nm bulk the LDD(Lightly Doped Drain) to minimize hot carrier generation can't be implemented in 28nm FDSOI. Furthermore, hot carrier reliability becomes worse with scaling, That is the major reason why 28nm FDSOI is not manufacturable today and will not be. Second, how can you suppress the leakage currents from such ultra short 7nm due to the short channel effects? How thin SOI thickness is required to prevent punch-through of un-dopped 7nm FDSOI? Possibly less than 4nm. Depositing such an ultra thin film less then 4nm filum uniformly and reliably over 12" wafers at the manufacturing line is extremely difficult or not even manufacturable. If not manufacturable, the 7nm FDSOI debate is over!Third, what happens when hot carriers are generated near the drain at normal operation of 7nm FDSOI? Electrons go to the positively biased drain with no harm but where the holes to go? The holes can't go to the substrate because of the thin BOX layer. Some holes may become trapped at the BOX layer causing Vt shift. However, the vast majority of holes drift through the the un-dopped SOI channel toward the N+Source,...
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