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Matthieu Wipliez
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Synflow makes RTL design obsolete
Matthieu Wipliez   9/13/2013 4:48:42 AM
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We have developed a new language and methodology for digital hardware design that removes the need for Register Transfer Level design.

Why? Because there is something wrong with RTL, and because High-Level Synthesis does not (and cannot) deliver the same performance as RTL design.

Our solution is hierarchical design of parallel tasks that are implemented in a C-based language dedicated for hardware. We have started to show videos of our software on our YouTube channel, feel free to take a look.

Let me know if you're interested (or if you're not, why !) :-)

Matthieu Wipliez, CTO and co-founder of Synflow, an EDA start-up company



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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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