Noticed denser interconnects in the A7, perhaps to accommodate the 2x wider ( 64 bit ) data and address buses within more or less the same real estate. Chipworks could go back and take one more look at their teardown of the Exynos 5 ( 32 bit 8 core ) in the Samsung S4 phone and compare the interconnect w/ the A7 ( both 28 nm by Sam ). Performance can actually take a hit if interconnect conductors & dielectrics are shrunk too much since resistance & capacitance will go up and will become a larger factor as the transistors get faster & more efficient.
@Tom - How did you determine that the NXP device shown is an LPC18xx device?
The A7 is about 10mm x 10 mm. About 4 of the LPC18A1s fit along one A7 edge. That means the device is about 2.5 mm x 2.5mm. If you look at the ball count, it is 5 x 6 with a 0.35mm pitch which is about 2.5 mm x 2.5 mm. A quick look at the datasheet shows the smallest LPC18xx is 100 balls with about 0.8mm pitch--nearly the same size as the A7. Clearly the device shown on the board is not nearly the same size as the A7--maybe 5% the area!
The math doesn't add up. Are you sure LPC18 and LPC18A1 = LPC18xx?
We did some poking around on the NXP website, looking at their LPC range of products; and we couldn't find any specific part that matched the look of the LPC18A1, particularly the 30-ball WLCSP packaging. So we've come to the tentative conclusion that this is likely a customised LPC18xx chip built for Apple, similar to those we've seen from Dialog and Cirrus over the years (A1 stands for Apple-1?).
Could be M3, could be M0 (though the latter don't have the LPC18 prefix).
Chip performance is important and. up to a certain stage multi-core matters.
But, I think that without a reasonable solution for managing the non-parallelizable fraction as described by Gustafson (http://en.wikipedia.org/wiki/Gustafson%27s_law) one cannot get reasonable scaling when the core count exceeds a point (last check it was 4 cores and at 8 one gets diminishing returns for SMP).
So, if SMP is used for more than 4 cores there is a liklihood that we are back to speed fro value. Of course, if there are some dataplane cores that are not within the SMP cluster then they can be removed from the parallizable portion provided they have a reasonable "look-aside" interaction with the other cores. However, that leaves the challenge of software syncronization. A challenge that is really best left to hardware by using one of a few known soltions that include hardware managed elastic interface (like queues or free memory pool management). Or a hardware scheduler can reduce the non-parallelizable portion if well implemented. I do not believe either of these are available on any existing ARM SoCs yet. I speculate that the interconnect/cross bar can be saturated on the 8 core design as well.
As a result, I think that the 2-64bit cores can perform well since it can gain from the larger register file. With the right bit-wize or vector instructions against the 64bit registers then the value increases since more data is registered for one operation.
It is simply a mystery how Apple and Samsung could be competitors and best of customers. You have Samsung make A7 chip which is there to knock-out Samsung products in the market. A unique case for business schools.
We at Chipworks will be reporting more details on the fingerprint sensor, M7 and the A7 in the coming week. Our team of industry experts are analysiing everything from the system level software and assemblies to the circuits and Process technology. As we have for the past 21 years, looking closely at the complex web of applicable Patents. Stay tuned. Tom @ Chipworks
Blog That A-Ha Moment Larry Desjardin 4 comments Have you ever had an a-ha moment? Sure, you have. The Merriam-Webster dictionary defines it as "a moment of sudden realization, inspiration, insight, recognition, or ...