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DrFPGA
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Building Blocks
DrFPGA   9/22/2013 11:44:52 PM
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It does seem like the basic definition of IP as a building block is the big problem. This locks you in to a bottom up approach. We need a "compiler" that can pull from the "library" of building block components and customize then as required to meet the high level requirements (speed, power, latency, etc). The tool would search thru the solution space to find a particular combination that fits the requirements (or comes back with a 'no solution' result). That's the direction I'd like to see things move...

garydpdx
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Re: Building Blocks
garydpdx   9/28/2013 8:20:36 PM
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In that case, please check us out, Space Codesign.  We have the capability of going to implementation after algorithm design and validation, and architecture design exploration.  Implementation can either map to libraries (e.g., Xilinx for FPGA) or to HLS (high level synthesis - Forte, Calypto, Xilinx, etc.) after design exploration figures out meeting your requirements.

By the way, Guy Bois, our president has a new blog article on this site discussing our approach.



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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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