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Susan Rambo
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Curious
Susan Rambo   9/24/2013 9:38:41 PM
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How unusual is it for a semiconductor company to sell 1 billion of anything?

_hm
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Configuration memory?
_hm   9/29/2013 7:58:51 AM
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Is configuration memory inside device or external to it? If it has internal configuration memory and live at power up, it may be very good for many more applications.

alex_m1
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Re: Configuration memory?
alex_m1   9/29/2013 5:41:30 PM
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It has internal config memory.

Brane212
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Check the facts...
Brane212   4/11/2014 9:57:54 PM
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Folks, do you even check basic facts about your stories ?

Lattice HAS NOT shipped out XO3. If you go to their site and click on FPGA->MachXO3, you'll see only 3 MachXO3L models. Which have NOTHING in common with MachXO3 in your article.

They have NO MIPI interface, no fast SERDES for PCIe, nothing even close to those claimed "540 I/O packages" etc etc.

They seem similar to old XO2, just constrained to a few packages in all but two related details.

And both of them are due to the fact that while XO2 had conventional FLASH that could be reprogrammed 10.000 times and had data endurance of 10 years, XO3 can be preogrammed only TWICE."

Consequently, it has no UFM User Flash memory Block ( UFB), since it has no FLASH that could be reprogrammed on board.

If you look closely on their page, they say with one sentence that basically what was promised initially ( and until not long ago) as MachXO3 is to come as MachXO3-H.

ice40 is all dandy for lowest power stuff but from what was promised as MachXO3, we have seen NOTHING so far.

Which doesn't mean we will not, ofcourse.

I'm just saying this is NOT YET it.

 



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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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