thank you Adele...no, I didn't realize that finFET was built on SOI substrate first!...since doing my research on SiGe devices while with U of Toronto in early 90-ties I have not been following basic transistor technology that closely...looking to hear from you on how finFET vs FDSOI debate continues at IEDM!...Kris
Kris, as of course as you know, FinFETs were originally developed on SOI - because it was easier! And there's that great animation on the SOI Consortium website that shows why that's still the case. But is easier necessarily in the interests of the foundries? If bulk FinFETs are more complicated but they get higher margins on them, it seems logical that's what they'll push...? Whereas for IDMs, they reap the savings (cheaper and easier) themselves. Not sure how good this trend would be for the industry, tho. On the other hand, we're starting to see some complaints from designers re: pain points in bulk FinFETS. Either way, looking forward to this IEDM for sure!
re: self-heating -- the paper summary indicates that they're looking at 6nm (!!) FD-SOI, and finding self-heating "comparable" to bulk FinFETs. So maybe not going away, but certainly not a show stopper!
note intel 14 Finfet now delayed. delay is more like a year for the volumn Broadwell release not the 3 months CEO stated. Broadwell will not be in volumn in market until end of 2014 and there is even talk Broadwell will be cancelled due to it being so late or a limited volumn release. my contact a copy manufacturing engineer says they are still not even involved in the manufacturing and he should of been involved 5 quarters ago.
My primary purpose was not to lower or higher number of FinFET or FDSOI papers in IEDM. FinFET is at high volume manufacturing now over 2 years at 22nm by Intel while FDSOI is not manufacturable at any technology node yet. Therefore, when FDSOI test chips become available, I propose the minimum requirements for measurement of the transistor electrical transfer characteristcs for both FinFET and FDSOI for fair comprison. The minimum requirements are posted in detail. SKim
michigan, so are you saying that despite much time there has not been enough progress in FinFET and this has led to lower number of papers in IEDM? But no other company apart from TSMC is presenting paper which means more companies are developing FDSOI. Don't u think.
I think your correct. FinFET sounded good but all the 3D process variation and high gate capacitance means many design blocks on the SOC have worse PPA. I think this is one of the reasons Apples 28nm A7 is much better than Intel's FinFET Bay Trail
Blog Doing Math in FPGAs Tom Burke 21 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...