I heard conflicting messages about this Kris (finFET vs FDSOI). Some say FDSOI controls leakage better than fitFET and is much easier to design. As such it will be the technology to succeed. Others say finFET is already the winner. I guess the proof of the pudding is in the eating....
Yes, they are very different technologies...finFET exploits silicon surface in a third dimension so you would expect every good Ion current but probably some difficulties in controlling Ioff...FDSoi takes advantage of thin silicon body so Ioff leakage is-likely easier to control but Ion values are not as good....so I think finFET will be better for high speed and FDSOI better for very low power...Kris
Here are some important facts about FDSOI technology. FDSOI was invented by IBM over a decade ago, but still not manufacturable at any technology node yet despite of enormous efforts and resouces were spent by IBM research and its International SOI consortium mainly because Soitec, the largest SOI wafer supplier can't deliver 7 nm thin SOI that is required for manufacturing of 28 nm FDSOI. AT 2011 SOI Conference at Phoenix, AZ Soitec announced that what it could deliver is 12 nm thin SOI wafer, not 7 nm SOI. For FDSOI at 20/22 nm an extremely thin 5 nm SOI is required to overcome the short channel effects or transistor leakage current. That is why FDSOI still not manufacturable even at 28nm today, and will not be manufacturable at 20/22 nm and beyond. FinFET is only technology in volume manufacturing for a couple of years at 22 nm by Intel, and 14 nm in late this year. TSMC appears to introduce its FinFET manufacturing in 2014. Beauty of FinFET is that it is extendable to the end of scaling according to FinFET physics. FDSOI can't contest with FinFET. There is alternative to FinFET today. Skim
Michigan0, the reason SOITEC delivers 12nm SOI wafer is not because they cannot deliver thinner wafers. It is simply because they are asked to do so. Any person familar with CMOS technology recongnizes that you need to consume a few nanometer to form STI (pad oxide needed before deposited pad nitride), then you need a few nanometer oxide for your I/O devices. Once you do the math, you realize that for a taget channel thickness of 6-7 nanometer you have to start somewhat thicker and this is exactly what has been asked from SOITEC and SEH. Unless you want to use deposited oxide for pad-ox and I/O devices (which is of course inferior to thermal oxide) this is what you'd need. Again, anybody that processed CMOS wafers knows that thermal oxidation is precisely controlled -- for our reference gate oxide was about 1nm thick with less than 5% variation before people switched to high-k.
As far as thickness control goes, in fact FDSOI has significant advantage over FinFET. The device is planar, which means you have a variety of well established methods to monitor thickness on as-received wafer and during processing, including ellipsometry and AFM. Metrology is a big problem with FinFET. Let alone the loading effects in depositing the spacer in SIT process and in etching the fins. Yes, FinFET is in mass production but I can say with enough confidence that it did NOT deliver the promissed 50% reduction in power that was claimed back in 2011 even after supposedly toc of Haswell.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.