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wilber_xbox
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Re: Nice job...
wilber_xbox   9/29/2013 12:53:51 PM
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Changing technology at 10nm will be too late. FinFET introduction has not given the advantage the companies thought it would due to complexity and litho limitation among many other things but i guess until someone else prove that FDSOI is better then companies will reconsider.

krisi
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Re: Nice job...
krisi   9/29/2013 11:52:45 AM
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I guess it is possible that at some point finFET would be build on Soi substrate, personally I don,t think that would happen...looks too complicated...there is no reasons why the two consortiums would not continue developing what they put massive r&d investments already in

Peter Clarke
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Re: Nice job...
Peter Clarke   9/29/2013 7:34:16 AM
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Yes, it is possible the two could meet in FinFET-over-insulator at atound 10nm.

Peter Clarke
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Re: Nice job...
Peter Clarke   9/29/2013 7:30:20 AM
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I think the issue with Intel is that the 14nm production is imminent and Intel does not need to share this information -- and so it does not.


In the case of TSMC 16nm FinFET and ST/GloFo 14nm FDSOI then these are foundry offerings that the companies have to SELL to customers as being reliable.

They are motivated to get the research out there.

 

Peter Clarke
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Re: Nice job...
Peter Clarke   9/29/2013 7:29:09 AM
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I think the issue with Intel is that the 14nm production is imminent and Intel does not need to share this information -- and so it does not.


In the case of TSMC 16nm FinFET and ST/GloFo 14nm FDSOI then these are foundry offerings that the companies have to SELL to customers as being reliable.

They are motivated to get the research out there.

 

Peter Clarke
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Re: Nice job...
Peter Clarke   9/29/2013 7:26:28 AM
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There is a paper within the IEDM program that takes another look at the self-heating problem. It definitely seems that it has not gone away.

In fact the FDSOI process is very well represented at IEDM suggesting that ST and partners are pushing hard.

 

KB3001
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CEO
Re: Nice job...
KB3001   9/29/2013 6:37:46 AM
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The fact finFET has not exactly delivered on the low power figures promised by Intel is giving FDSOI renewed momentum.

resistion
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CEO
Re: Nice job...
resistion   9/29/2013 6:26:05 AM
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So much renewed confidence in FD-SOI..so is the self-heating issue now resolved?

AKH0
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Manager
Re: FinFET vs.FDSOI
AKH0   9/29/2013 3:47:47 AM
Michigan0, the reason SOITEC delivers 12nm SOI wafer is not because they cannot deliver thinner wafers. It is simply because they are asked to do so. Any person familar with CMOS technology recongnizes that you need to consume a few nanometer to form STI (pad oxide needed before deposited pad nitride), then you need a few nanometer oxide for your I/O devices. Once you do the math, you realize that for a taget channel thickness of 6-7 nanometer you have to start somewhat thicker and this is exactly what has been asked from SOITEC and SEH. Unless you want to use deposited oxide for pad-ox and I/O devices (which is of course inferior to thermal oxide) this is what you'd need. Again, anybody that processed CMOS wafers knows that thermal oxidation is precisely controlled -- for our reference gate oxide was about 1nm thick with less than 5% variation before people switched to high-k.


As far as thickness control goes, in fact FDSOI has significant advantage over FinFET. The device is planar, which means you have a variety of well established methods to monitor thickness on as-received wafer and during processing, including ellipsometry and AFM. Metrology is a big problem with FinFET. Let alone the loading effects in depositing the spacer in SIT process and in etching the fins. Yes, FinFET is in mass production but I can say with enough confidence that it did NOT deliver the promissed 50% reduction in power that was claimed back in 2011 even after supposedly toc of Haswell.

 

michigan0
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CEO
FinFET vs.FDSOI
michigan0   9/28/2013 6:19:51 PM
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one correction posted below by michigan: The last sentence should be read,  no alternative to FinFET today instead of alternative to FinFET today.

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