It's a fair comment about the STT-MRAM. Plus the etching is always a concern from the process point of view, the difficulty of STT-MRAM as for SRAM/DRAM application is getting higher at more advaced nodes. And at the mainstream and old technology nodes, no demand to replace DRAM/SRAM with STT-MRAM either. So kind of subtle situation for STT-MRAM.
Memristor was the name ascribed to a theoretical two terminal variable resistence device by Leon Chua. The term was picked up and used by Hewlett-Packard who have worked on two-terminal memories.
However, in practice the landscape is very complex with numerous different materials systems being studied and the possibiity of multiple physical, chemical and quantum mechanical effects in play at the same time.
Although its write endurance is sufficient, it needs to demonstrate reliable read endurance as a SRAM or DRAM replacement. This will be hard to do for a fast read current, since read disturb is becoming more likely.
Another difficulty is the resistance-area product which is quite low at ~10 ohm-um2. In that case, the transistor must always be bigger than the MTJ, which is hard to sell. But for advanced nodes, even the interconnect resistance will be of the same order of magnitude.
So I think its burden for entry is quite high and getting higher.
As noted in the abstracts the on/off ratios of the devices in the 3D-RRAMs are still on the order of 100-1000 at best. That is hardly worth bragging. Also, some 3D-RRAM current densities (e.g., IMEC) are too high.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.