Thanks - skeptic. There is much information in your reply.
I just read several papers on this. It is interesting to find that even the whole paper is talking about a phenomenon which can be explained by the known classical semiconductor physics principles, there is always a "memristor" word in the title. For example, the papers from one group from the University of Michigan, who recently announced the release of a chip based on such a concept (a so-called Crossbar comapny).
"Memristor" looks like a new thing from "resistor, capacitor and inductor", but unfortunately I can find nothing new in these papers. They talked the same thing in the textbooks. I'm wondering whether they really understand what "memristor" means before they put this new word in their papers.
What is called "resistance switching" is a sort of phenomena. Under certain conditions, "resistance switching" behavior can be brought about in various metal/insulator/metal structures after a soft-breakdown of the insulating material has occurred. Such effects could offer the potential for nonvolatile memory applications (ReRAM or RRAM). "Resistance switching" phenomena are well known since decades /1/ and are in no way related to the concept of "memristor/memristive" systems. Nevertheless, there is ongoing research because there are still a lot of questions with respect to the underlying physical mechanisms. Understanding into the probabilistic nature of the "resistance switching" operation is, for example, crucial to get grip on reliability issues of ReRAM devices.
What is called "memristor" is a sort of hypothetical concept. "Memristors" are conceptually defined by a unique set of characteristic mathematical state equations – based on the mathematical framework proposed by L. Chua /2/. Thus, solid state memory devices should only be labeled "memristors" if one is able to propose a reasonable physical model that satisfies these state equations.
Any scientific evidence that "memristors" might exist in physical reality is missing so far. HP's "memristor" model which was presented in 2008 in the NATURE paper "The missing memristor found" /3/ is, e.g., based on severe electrochemical misconceptions: one cannot derive the characteristic dynamic state equations of a "memristor" on base of HP's dopant drift model, i.e., no memory devices can operate in accordance with the model because the model is by itself in conflict with fundamentals of electrochemistry /4/. Thus, up to now nobody has invented or found a memory device which operates like a genuine nonvolatile "memristor".
Moreover, the nonvolatile "memristor" concept raises some severe questions when viewed from the perspective of non-equilibrium thermodynamics /4, 5/. Nonvolatile information storage requires the existence of energy barriers that separate distinct memory states from each other. "Memristors" whose resistance (memory) states depend only on the current (like the HP memristor) or voltage history would thus be unable to protect their memory states against unavoidable fluctuations and therefore permanently suffer information loss:the proposed hypothetical concept provides no physical mechanism enabling such systems to retain memory states after the applied current or voltage stress is removed. Such elements can therefore not exist, as they would always be susceptible to a so-called "stochastic catastrophe" /5/. It is therefore pointless to tinker with this concept in order to describe physical phenomena like "resistance switching" effects.
It's a fair comment about the STT-MRAM. Plus the etching is always a concern from the process point of view, the difficulty of STT-MRAM as for SRAM/DRAM application is getting higher at more advaced nodes. And at the mainstream and old technology nodes, no demand to replace DRAM/SRAM with STT-MRAM either. So kind of subtle situation for STT-MRAM.
Memristor was the name ascribed to a theoretical two terminal variable resistence device by Leon Chua. The term was picked up and used by Hewlett-Packard who have worked on two-terminal memories.
However, in practice the landscape is very complex with numerous different materials systems being studied and the possibiity of multiple physical, chemical and quantum mechanical effects in play at the same time.
Although its write endurance is sufficient, it needs to demonstrate reliable read endurance as a SRAM or DRAM replacement. This will be hard to do for a fast read current, since read disturb is becoming more likely.
Another difficulty is the resistance-area product which is quite low at ~10 ohm-um2. In that case, the transistor must always be bigger than the MTJ, which is hard to sell. But for advanced nodes, even the interconnect resistance will be of the same order of magnitude.
So I think its burden for entry is quite high and getting higher.