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Ron Neale
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Vaporizing carbon
Ron Neale   9/30/2013 12:39:54 PM
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Carbon melts at approx 3600 C and vaporizes (boils) at 4200 C. They state "..vaporize them -- like a fuse -- thus cleansing the circuitry of all but the remaining semiconducting nanotubes..." It is to be hoped that this operation is carried out in an oxygen rich atmosphere as this will allow lower temperatures with the by- products carbon monoxide or dioxide and avoid, as might be the case with fusing, a field of carbon debris spreading over the rest of the wafer.  Is this step carried out a wafer probe test time?

R_Colin_Johnson
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Re: Vaporizing carbon
R_Colin_Johnson   9/30/2013 1:09:24 PM
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The metallic nanotube removal process is performed before the etching step which defines the standard cells. Here what they told me about VLSI-compatible Metallic CNT Removal (VMR) in an email: "The process begins by depositing a special interdigited layout structure on the wafer containing a mixture of metallic and semiconducting CNTs.  These interdigitated fingers are patterned at the minimum lithographic pitch (parts of it will become the final source and drain contacts in the circuit).  Electrical breakdown is performed once on the entire VMR structure, removing all metallic CNTs within the entire structure...After breakdown, sections of the VMR structure are etched out, leaving the contacts which will remain for the final circuit."

wilber_xbox
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technology node
wilber_xbox   9/30/2013 3:01:41 PM
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So, which technology node can we implement this solution. We are still looking for ideas for 10nm and below and this reseach advancement might have come at the right time.

R_Colin_Johnson
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Re: technology node
R_Colin_Johnson   9/30/2013 3:14:52 PM
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A single carbon nanotube could form a transistor channel as narrow as a single nanometer, but this technique uses many in parallel to form a single transistor channel by patterning at the lithographic limit of whatever process is being used. The researchers did not speculate on the node at which it would be prudent to implement their technology. Their next step is to characterize the speed and energy efficiency of their technique.

Frank Eory
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Re: Vaporizing carbon
Frank Eory   9/30/2013 6:40:08 PM
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Electrical breakdown followed by an etch doesn't sound quite like "vaporizing."

R_Colin_Johnson
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Re: Vaporizing carbon
R_Colin_Johnson   9/30/2013 6:59:40 PM
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The press materials say the metallic nanotubes grow so hot that they "literally vaporize into tiny puffs of carbon dioxide"

RobDinsmore
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Rookie
Re: technology node
RobDinsmore   10/1/2013 11:27:56 AM
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10nm is already well into development at Intel, with all candidate process tools in place or set to be installed before the end of the year and something like this would take many years to become viable.  First equipment vendor(s) would have to be working on this for atleast a couple of quarters.  There are several steps involved and working with quartz substrates may lead to issues.      

Intel seems to think they can extend "traditional" CMOS to the 5nm node which should be ramping up in Hillsboro in 6 years.  However this technology may actually qualify as traditional so I cannot really comment on anything that far off.  But 10nm is not going to bring CNTs to the desktop.   

 

jaybus0
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CEO
Re: Vaporizing carbon
jaybus0   10/2/2013 6:53:52 AM
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How tightly packed are the CNTs? How does the extreme heat of vaporizing a metallic CNT not affect adjacent semiconductor CNTs?

rpcy
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Re: technology node
rpcy   10/2/2013 8:27:05 PM
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The part about running 20 instructions from the MIPS instruction set is incorrect, or at least very misleading. This demo runs one and only one instruction, the SUBNEG instruction, from which all other instructions can, in principle, be synthesized. What the Stanford guys have done is really cool, but let's be clear about exactly what it was.

 

R_Colin_Johnson
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Re: technology node
R_Colin_Johnson   10/3/2013 7:58:48 AM
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@rpcy "This demo runs one and only one instruction, the SUBNEG instruction, from which all other instructions can, in principle, be synthesized"

Thanks for the clarificaition. I guess we could say this proof of concept demo is the ultimate reduced instruciton set computer. It reminds me of early Cray supercomputers which used NAND gates to synthesize all their instructions.

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