Design Con 2015
Breaking News
Comments
Newest First | Oldest First | Threaded View
<<   <   Page 3 / 4   >   >>
daleste
User Rank
CEO
Re: Show me the 20nm
daleste   10/3/2013 11:14:52 PM
NO RATINGS
Not surprising to see TSMC pushing forward to smaller technologies. With the number of wafers they process, they have the volume to push the envelope. The great thing is the number of companies that will benefit from this advancement.

rick merritt
User Rank
Author
Re: Show me the 20nm
rick merritt   10/3/2013 2:08:33 PM
NO RATINGS
@dynamited: Good point on apparent lack of 3 GHz IP s far at 20nm.

Many of the major 28nm designs used PCIe Gen 3. Pewrhpas they will skip 20 and go for 16?

rick merritt
User Rank
Author
Re: 20nm costs
rick merritt   10/3/2013 2:06:02 PM
NO RATINGS
@jamespcwang: I don't follow the EDA side closely but you capture the issue of rising complexity for chip designers beautifully with the metrics below:

65nm with 800 rules, 20k deck size;

20nm 3k, 80k; and 16nm 3.4k, 100k)

28HPM at 280 corners and 16FinFET 360 corners and so many analog circuit to redesign (100% redesign at 16FinFET)

 

Wow!


rick merritt
User Rank
Author
Re: 20nm costs
rick merritt   10/3/2013 1:59:14 PM
NO RATINGS
@ScottenJ: Thanks for the i nsightful comments and good future questions for TSMC!

I'll be at IMEC next week and hope for an update on EUV among othewr things.

AKH0
User Rank
Manager
Re: 20nm costs
AKH0   10/3/2013 12:46:29 PM
NO RATINGS
Wondering if the power saving numbers are backed by Si or are just model numbers. Back in 2011 we heard claims of 50% power reduction and what was shown in product was about 20% at high end and almost no change for low power parts.

ScottenJ
User Rank
Rookie
Re: 20nm costs
ScottenJ   10/3/2013 12:41:49 PM
NO RATINGS
James

TSMC's gate last HKMG will continue to be used at 20nm and 16nm, it wasn't just for 28nm.

Additional comments relevent to this thread:

The key issue right now it the lateness of EUV which is making shrinks much harder and more expensive. TSMC's 20nm will be a full shrink with some cost reduction, 16nm is essentially no shrink and a big increase in die cost so only customers who need performance are likely to use it. At 10nm - hopefully with EUV we should see a full shrink again with a full cost reduction.

It does look like Multigate is the leading technology for 16nm/14nm and below. FDSOI/ETSOI appears to be a low power/RF niche technology to me.

Please note I say multigate and not finFET. A classic finFET is a fin with gates on both sides. Intel's Trigate is a fin with gates on the top and both sides, that is a significant difference. For Trigate you have to deal with the high electric field at the top corners but you also get to relax the fin width.

For fully depleted operation SOI silicon thickness has to be 1/3 the gate length and that is really hard to do as gate lengths scale down. For finFETs with 2 gates the fin width must be 1/2 the gate length. For TriGate the fin width is 1x the gate length making manufacturing easier.

It will be interesting to see whether TSMC makes a classic 2 gate finFET or a 3 gate Trigate.

krisi
User Rank
CEO
Re: 20nm costs
krisi   10/3/2013 12:23:23 PM
NO RATINGS
Carbon nanotubes have long ways to go...no need to involve them in this short term discussion

jamescpwang
User Rank
Freelancer
Re: 20nm costs
jamescpwang   10/3/2013 5:08:24 AM
NO RATINGS
Compared to 20HKMG, 16FinFET's value is 20% better speed or 35% less power consumption. There's no density advantage migrating from 20nm to 16nm and the Cost per area/die will go up at 16nm. All supply chain members must implement continuous cost cutting program to accommodate the higher cost.

It's a good idea for tsmc by achieving 16nm development with 20nm development as a stepping stone. Combining too many revolutionary BEOL (metal double patterning) and FEOL (FinFET) variables in one development may result in much longer development time.

Significantly revised design flows with so many new design rules to follow (65nm with 800 rules, 20k deck size; 20nm 3k, 80k; and 16nm 3.4k, 100k), so many new simulation corners to signoff (28HPM at 280 corners and 16FinFET 360 corners) and so many analog circuit to redesign (100% redesign at 16FinFET), it's good to have two nodes for designers to migrate smoothly.

It's a big waste if the complicated gate-last HKMG technology has been used in only one node at 28nm, especially for tsmc with overwhelming market share win at the HKMG node.

AnySilicon
User Rank
Freelancer
FinFET
AnySilicon   10/3/2013 3:14:18 AM
NO RATINGS
Seems like FinFET willl be the leading technology for 20nm and below.

jamescpwang
User Rank
Freelancer
Re: Show me the 20nm - yield
jamescpwang   10/3/2013 3:07:18 AM
NO RATINGS
In the slide "20Soc Value Proposition", demonstrated 20nm 112M HD SRAM nature yield of > 75%. The same nature yield of 16nm FinFET 128Mb HC SRAM.

<<   <   Page 3 / 4   >   >>


Top Comments of the Week
Flash Poll
Like Us on Facebook

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
EE Life
Frankenstein's Fix, Teardowns, Sideshows, Design Contests, Reader Content & More
<b><a href=Betajet">

The Circle – The Future's Imperfect in the Present Tense
Betajet
5 comments
The Circle, a satirical, dystopian novel published in 2013 by San Francisco-based writer Dave Eggers, is about a large, very powerful technology company that combines aspects of Google, ...

Max Maxfield

Recommended Reads From the Engineer's Bookshelf
Max Maxfield
27 comments
I'm not sure if I read more than most folks or not, but I do I know that I spend quite a lot of time reading. I hate to be idle, so I always have a book or two somewhere about my person -- ...

Martin Rowe

Make This Engineering Museum a Reality
Martin Rowe
Post a comment
Vincent Valentine is a man on a mission. He wants to make the first house to ever have a telephone into a telephone museum. Without help, it may not happen.

Rich Quinnell

Making the Grade in Industrial Design
Rich Quinnell
16 comments
As every developer knows, there are the paper specifications for a product design, and then there are the real requirements. The paper specs are dry, bland, and rigidly numeric, making ...

Special Video Section
The LT8640 is a 42V, 5A synchronous step-down regulator ...
The LTC2000 high-speed DAC has low noise and excellent ...
How do you protect the load and ensure output continues to ...
General-purpose DACs have applications in instrumentation, ...
Linear Technology demonstrates its latest measurement ...
10:29
Demos from Maxim Integrated at Electronica 2014 show ...
Bosch CEO Stefan Finkbeiner shows off latest combo and ...
STMicroelectronics demoed this simple gesture control ...
Keysight shows you what signals lurk in real-time at 510MHz ...
TE Connectivity's clear-plastic, full-size model car shows ...
Why culture makes Linear Tech a winner.
Recently formed Architects of Modern Power consortium ...
Specially modified Corvette C7 Stingray responds to ex Indy ...
Avago’s ACPL-K30T is the first solid-state driver qualified ...
NXP launches its line of multi-gate, multifunction, ...
Doug Bailey, VP of marketing at Power Integrations, gives a ...
See how to ease software bring-up with DesignWare IP ...
DesignWare IP Prototyping Kits enable fast software ...
This video explores the LT3086, a new member of our LDO+ ...
In today’s modern electronic systems, the need for power ...