Not surprising to see TSMC pushing forward to smaller technologies. With the number of wafers they process, they have the volume to push the envelope. The great thing is the number of companies that will benefit from this advancement.
Wondering if the power saving numbers are backed by Si or are just model numbers. Back in 2011 we heard claims of 50% power reduction and what was shown in product was about 20% at high end and almost no change for low power parts.
TSMC's gate last HKMG will continue to be used at 20nm and 16nm, it wasn't just for 28nm.
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The key issue right now it the lateness of EUV which is making shrinks much harder and more expensive. TSMC's 20nm will be a full shrink with some cost reduction, 16nm is essentially no shrink and a big increase in die cost so only customers who need performance are likely to use it. At 10nm - hopefully with EUV we should see a full shrink again with a full cost reduction.
It does look like Multigate is the leading technology for 16nm/14nm and below. FDSOI/ETSOI appears to be a low power/RF niche technology to me.
Please note I say multigate and not finFET. A classic finFET is a fin with gates on both sides. Intel's Trigate is a fin with gates on the top and both sides, that is a significant difference. For Trigate you have to deal with the high electric field at the top corners but you also get to relax the fin width.
For fully depleted operation SOI silicon thickness has to be 1/3 the gate length and that is really hard to do as gate lengths scale down. For finFETs with 2 gates the fin width must be 1/2 the gate length. For TriGate the fin width is 1x the gate length making manufacturing easier.
It will be interesting to see whether TSMC makes a classic 2 gate finFET or a 3 gate Trigate.
Compared to 20HKMG, 16FinFET's value is 20% better speed or 35% less power consumption. There's no density advantage migrating from 20nm to 16nm and the Cost per area/die will go up at 16nm. All supply chain members must implement continuous cost cutting program to accommodate the higher cost.
It's a good idea for tsmc by achieving 16nm development with 20nm development as a stepping stone. Combining too many revolutionary BEOL (metal double patterning) and FEOL (FinFET) variables in one development may result in much longer development time.
Significantly revised design flows with so many new design rules to follow (65nm with 800 rules, 20k deck size; 20nm 3k, 80k; and 16nm 3.4k, 100k), so many new simulation corners to signoff (28HPM at 280 corners and 16FinFET 360 corners) and so many analog circuit to redesign (100% redesign at 16FinFET), it's good to have two nodes for designers to migrate smoothly.
It's a big waste if the complicated gate-last HKMG technology has been used in only one node at 28nm, especially for tsmc with overwhelming market share win at the HKMG node.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.