The single vs double pipeline is obviously the key difference between a 486 and a Pentium. Also note that the 486 and Quark have a single cache, while the Pentium has split code and data caches. Both 486 and Quark use a 128-bit fetch bus and a 32-bit data bus, while Pentium uses a 256-bit fetch bus and a 64-bit data bus. Finally the Pentium has a branch target buffer, which neither the 486 nor Quark have. So it's 100% certain that Quark is a 486, not a slimmed down Pentium.
I did take a look at the block diagrams, and to be honest it was all there roughly connected the same way. Some of the blocks have been physically shifted around to make it look prettier, but they were there. I started with the control unit and compared between the two what was connected to that. I was able to identify that each of the blocks was consistent, with slight nomenclature differences. Some showed more of a breakdown of intercomponents in each generic block. The quark also has the 64bit interunit transfer bus that is found on the pentium architecture. The main difference that I see is that there is a single 5 stage pipeline as opposed to two 5 stage pipelines.
I'm guessing that Intel meant with "Pentium class performance" is that at 400MHz Quark achieves similar performance as the original Pentium did. That's a reasonable statement as 20 year old Pentiums were pretty slow, but it doesn't imply at all that Quark itself is a Pentium.
I agree about the other areas, it's a very complex CPU for what little it does.
Well if it's not scanning for marketing terms then I don't understand how you could think it is an out-of-order Pentium (ie. a Pentium Pro!). For example the word "out-of-order" only occurs in the section about the memory controller. It's normal for a memory controller to reorder memory requests. But that doesn't make a CPU out-of-order!
Please do not misunderstand. I have other areas where I am disappointed in the Quark chip. I just do not see where you are pulling out of the datasheet itself that this is a 486 chip. This combined with statements from Intel that this is in the performance class of a Pentium make me probe statements to the contrary a bit more.
The things that make me disappointed about the chip are the fact that the peripherals are rather lackluster. They have few timers as well as timers that are missing a lot of features. The chip is also complex. Having 5 separate voltage requirements for an embedded chip is a bit ridiculous. Another area is the datasheet. To get data from the datasheet, you really have to dig compared to datasheets from other vendors. Lastly, there is little information about power consumption. This was something that Intel was touting, but all you find is a table that lists the max power supply requirements for all the different power rails. This is further complicated by the complex power states and no information on normal power consumption levels. Lastly, the fact that there is no mention of any sort of benchmark comparison in the datasheet or other supporting documents is also disappointing.
Sorry but you're clinging on to some Intel marketing words and not actually reading the manuals. Neither the 486 and Pentium are out-of-order - going out of order doesn't make any sense at all when you are aiming for small size and low power consumption.
Of course we'll have to run actual benchmarks on Quark to be sure, but the cycle counts and memory system simply do not look good on paper. Neither does the power consumption - for example the SAMA5D3 I mentioned uses just 200mW at max frequency with all perhiperhals enabled. That's on a 65nm process...
Your numbers on the math side add up, but the claim that it is a 486 do not. As I understand it the 486 never had out of order execution, which this device does (noted in section 1.2.2 of the second link). The other is that this device specifically handles the Pentium instruction set. It is noted in section 11 of the second document that you linked. If it is correct that this then is a Pentium class device, then as I understand it, that would put it at around 1.9 DMIPS/MHz (sources conflict on this number, but most of them were close to this number). This would compare favorably to the A7 and A8 devices.
Perhaps some of the peripherals that Intel would invite others to integrate into branded chips would be a MAC so as to reduce the math ops clock counts. That seems a little deeper integration than I would expect. This could also just be a first generation device. At 1.9DMIPS/MHz, that puts it in a competative range for performance, one would just have to see the power draw. From the TPD numbers that may be high as well, but I have a feeling that comes due to the support of the PCIe connections. I think that the core numbers are lower than that, but I have not received any information on this from Intel.
Blog Doing Math in FPGAs Tom Burke 23 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...