I watched/listened to a video interview in the past year given by Debra Vogler, in that interview An gave enough reasons to show why EUV is basically "out there" forever, saving my efforts. Dragging N10 and N7 nodes to a decade or longer, is "out there" forever.
For the memory portion, I was a bit surprised that there was not more focus on vertical NAND or future vertical 3D-NVM. That technology has just recently been announced, while FinFETs have been around much longer.
Also, why so much focus on STT-MRAM? They should know it is quite a fragile device. More fragile than a transistor at leading edge. The read is not 100% non-destructive, for the spec that is expected (quadrillion times).
"Immersion systems may need 22 masks at 10nm, up from ten at 28nm, essentially using costly triple patterning in a handful of layers and double patterning at all others. EUV could cut that down to ten masks at 10nm, researchers estimate."
So, again confirming, essentially just one node (10 nm) for EUV single patterning. Same situation faced 157 nm, with far less drastic infrastructure changes required.
I nelgected to note IMEC's CTO told me in the last year one of the programs that got the most ramping up at IMEC was on direct self assembly which they now show in their road map as having a significant role at 5nm helping beyond what EUV can/cannot do.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.