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resistion
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An's being generous to EUV
resistion   10/9/2013 8:02:08 AM
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I watched/listened to a video interview in the past year given by Debra Vogler, in that interview An gave enough reasons to show why EUV is basically "out there" forever, saving my efforts. Dragging N10 and N7 nodes to a decade or longer, is "out there" forever.

resistion
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Re: An's being generous to EUV
resistion   10/9/2013 10:55:44 PM
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"Immersion systems may need 22 masks at 10nm, up from ten at 28nm, essentially using costly triple patterning in a handful of layers and double patterning at all others. EUV could cut that down to ten masks at 10nm, researchers estimate."

So, again confirming, essentially just one node (10 nm) for EUV single patterning. Same situation faced 157 nm, with far less drastic infrastructure changes required.

rick merritt
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Re: An's being generous to EUV
rick merritt   10/10/2013 3:50:13 AM
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Note: IMEC sees EUV helping reduce double and triple patterning at 7nm, too, but not eliminating it

resistion
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LOCSOI
resistion   10/9/2013 5:47:26 PM
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7 nm shows LOCSOI - is that local SOI?

rick merritt
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Re: LOCSOI
rick merritt   10/10/2013 3:49:14 AM
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@Resistion" Good question, but I don't have a good answer. I'l ask An to weigh in

AKH0
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14nm FDSOI
AKH0   10/9/2013 7:00:57 PM
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To be clear, IMEC never really worked on 14nm FDSOI. This was developed by IBM-ST-Leti alliance. So, it really doen't mean anything if its is shown on IMEC's roadmap or not.

resistion
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memory part
resistion   10/9/2013 10:29:41 PM
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For the memory portion, I was a bit surprised that there was not more focus on vertical NAND or future vertical 3D-NVM. That technology has just recently been announced, while FinFETs have been around much longer.

Also, why so much focus on STT-MRAM? They should know it is quite a fragile device. More fragile than a transistor at leading edge. The read is not 100% non-destructive, for the spec that is expected (quadrillion times).

rick merritt
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Re: memory part
rick merritt   10/10/2013 3:51:26 AM
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@Resistion: I did not go into a welath of material An presented about flash including the move to 3-D structures. But that info is implicit in the two memory foils if you look closely.

resistion
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Re: memory part
resistion   10/10/2013 4:56:48 AM
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Ok, I see 3D-SONOS, but STT still seems to be more all over the place. Of course worth looking at, but I think they're starting late.

resistion
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Re: memory part
resistion   10/10/2013 10:11:01 AM
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Samsung (IMEC member) alone seems to have its own drive for STT-MRAM research with its Global MRAM Innovation program: http://www.samsung.com/global/business/semiconductor/news-events/mram#!

 

rick merritt
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DSA
rick merritt   10/10/2013 3:52:56 AM
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I nelgected to note IMEC's CTO told me in the last year one of the programs that got the most ramping up at IMEC was on direct self assembly which they now show in their road map as having a significant role at 5nm helping beyond what EUV can/cannot do.

any1
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Re: DSA
any1   10/10/2013 9:16:09 AM
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Directed self assembly has made rapid progress in the last few years.  Since it looks like EUV will miss being implemented at the 10 nm node for leading edge companies like Intel, it's now looking like some sort of complimentary lithography scheme using DSA might be ready by the 7 or 5 nm nodes.

michigan0
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IMEC's road map
michigan0   10/16/2013 5:59:21 PM
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Why dose IMEC roadmap include FDSOI at 14nm today if it will 

drop it beyond 14nm? FDSOI was invented by IBM over a 

decade ago, but still not manufacturable at any technology 

node yet, including FDSOI at 35 and 28nm. 28nm Bulk Si is in 

mass production  for several years by major semiconductor

 companies.

 

Ge or InGaAs replacement processes are extremely difficult to

 be implemented in FinFET manufacturing. I do not think such

 replacement processes are necessary to enhance

 FinFET performance. SKim



resistion
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Single patterning ain't coming back
resistion   10/17/2013 8:23:09 AM
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1 saves
Even the EUV community is saying DP is necessary, DP cost has to come down.

john-F
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EUV slip
john-F   10/20/2013 11:17:24 AM
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how come no one is calling EUV program out on recent slip. ASML was suppose to ship like 5 80W source tools this year. Now that has been reduced to 1 and the new target for source power is 70W in 2014. EUV has missed 10nm or 9nm what what ever you want to call the node in 2017 after 14/16

resistion
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Re: EUV slip
resistion   10/20/2013 12:18:20 PM
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You're right, just read this: http://m.seekingalpha.com/article/1748582

 



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