I watched/listened to a video interview in the past year given by Debra Vogler, in that interview An gave enough reasons to show why EUV is basically "out there" forever, saving my efforts. Dragging N10 and N7 nodes to a decade or longer, is "out there" forever.
"Immersion systems may need 22 masks at 10nm, up from ten at 28nm, essentially using costly triple patterning in a handful of layers and double patterning at all others. EUV could cut that down to ten masks at 10nm, researchers estimate."
So, again confirming, essentially just one node (10 nm) for EUV single patterning. Same situation faced 157 nm, with far less drastic infrastructure changes required.
For the memory portion, I was a bit surprised that there was not more focus on vertical NAND or future vertical 3D-NVM. That technology has just recently been announced, while FinFETs have been around much longer.
Also, why so much focus on STT-MRAM? They should know it is quite a fragile device. More fragile than a transistor at leading edge. The read is not 100% non-destructive, for the spec that is expected (quadrillion times).
I nelgected to note IMEC's CTO told me in the last year one of the programs that got the most ramping up at IMEC was on direct self assembly which they now show in their road map as having a significant role at 5nm helping beyond what EUV can/cannot do.
Directed self assembly has made rapid progress in the last few years. Since it looks like EUV will miss being implemented at the 10 nm node for leading edge companies like Intel, it's now looking like some sort of complimentary lithography scheme using DSA might be ready by the 7 or 5 nm nodes.
how come no one is calling EUV program out on recent slip. ASML was suppose to ship like 5 80W source tools this year. Now that has been reduced to 1 and the new target for source power is 70W in 2014.
EUV has missed 10nm or 9nm what what ever you want to call the node in 2017 after 14/16