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rick merritt
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rick merritt   10/10/2013 3:49:14 AM
@Resistion" Good question, but I don't have a good answer. I'l ask An to weigh in

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Re: An's being generous to EUV
resistion   10/9/2013 10:55:44 PM
"Immersion systems may need 22 masks at 10nm, up from ten at 28nm, essentially using costly triple patterning in a handful of layers and double patterning at all others. EUV could cut that down to ten masks at 10nm, researchers estimate."

So, again confirming, essentially just one node (10 nm) for EUV single patterning. Same situation faced 157 nm, with far less drastic infrastructure changes required.

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memory part
resistion   10/9/2013 10:29:41 PM
For the memory portion, I was a bit surprised that there was not more focus on vertical NAND or future vertical 3D-NVM. That technology has just recently been announced, while FinFETs have been around much longer.

Also, why so much focus on STT-MRAM? They should know it is quite a fragile device. More fragile than a transistor at leading edge. The read is not 100% non-destructive, for the spec that is expected (quadrillion times).

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14nm FDSOI
AKH0   10/9/2013 7:00:57 PM
To be clear, IMEC never really worked on 14nm FDSOI. This was developed by IBM-ST-Leti alliance. So, it really doen't mean anything if its is shown on IMEC's roadmap or not.

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resistion   10/9/2013 5:47:26 PM
7 nm shows LOCSOI - is that local SOI?

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An's being generous to EUV
resistion   10/9/2013 8:02:08 AM
I watched/listened to a video interview in the past year given by Debra Vogler, in that interview An gave enough reasons to show why EUV is basically "out there" forever, saving my efforts. Dragging N10 and N7 nodes to a decade or longer, is "out there" forever.

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