Warrior is basically an A15 clone which uses NVidia's 4+1 approach rather than big.Little (however you're right that by the time Warrior comes out it'll have to compete with the 64-bit A57/A53).
The 30% smaller size is based on a comparison with the 28nm Octa core - however its consists of mostly L2 cache (66%). TSMC has smaller SRAMs, so if Warrior actually has a 30% smaller CORE (rather than a more dense L2) then that would be impressive - certainly if it also gives A15-class performance. But given the comparison I doubt it. See this for an interesting core comparison: http://chip-architect.com/news/2013_core_sizes_768.jpg
Also interesting to see they had to do macro-op fusion to combine 2 loads/stores instead of adding LDRD/STRD instructions like ARM did. I don't think they will ever be comparing MIPS with ARM on codesize!
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.