Warrior is basically an A15 clone which uses NVidia's 4+1 approach rather than big.Little (however you're right that by the time Warrior comes out it'll have to compete with the 64-bit A57/A53).
The 30% smaller size is based on a comparison with the 28nm Octa core - however its consists of mostly L2 cache (66%). TSMC has smaller SRAMs, so if Warrior actually has a 30% smaller CORE (rather than a more dense L2) then that would be impressive - certainly if it also gives A15-class performance. But given the comparison I doubt it. See this for an interesting core comparison: http://chip-architect.com/news/2013_core_sizes_768.jpg
Also interesting to see they had to do macro-op fusion to combine 2 loads/stores instead of adding LDRD/STRD instructions like ARM did. I don't think they will ever be comparing MIPS with ARM on codesize!
A Book For All Reasons Bernard Cole1 Comment Robert Oshana's recent book "Software Engineering for Embedded Systems (Newnes/Elsevier)," written and edited with Mark Kraeling, is a 'book for all reasons.' At almost 1,200 pages, it ...