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elctrnx_lyf
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Warrior
elctrnx_lyf   10/19/2013 8:52:21 AM
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Imaginations has a very strong expertise and past experience in the development of graphic cores. They see to be really in full control of the future.

Wilco1
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It's not big.Little but NVidia's 4+1
Wilco1   10/15/2013 6:09:37 PM
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Warrior is basically an A15 clone which uses NVidia's 4+1 approach rather than big.Little (however you're right that by the time Warrior comes out it'll have to compete with the 64-bit A57/A53).

The 30% smaller size is based on a comparison with the 28nm Octa core - however its consists of mostly L2 cache (66%). TSMC has smaller SRAMs, so if Warrior actually has a 30% smaller CORE (rather than a more dense L2) then that would be impressive - certainly if it also gives A15-class performance. But given the comparison I doubt it. See this for an interesting core comparison: http://chip-architect.com/news/2013_core_sizes_768.jpg

Also interesting to see they had to do macro-op fusion to combine 2 loads/stores instead of adding LDRD/STRD instructions like ARM did. I don't think they will ever be comparing MIPS with ARM on codesize!



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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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