I wonder if TSMC is now doing REAL 3-d stack ( i,e. TSVs in active dice and stacking them ) or still just 2.5-d ( NO TSVs in the active dice, no active die on top of another ) like their earlier Vertex modules for Xilinx.
Your point about difficulty is however well taken. It took Micron at least 2 years to start sampling their HMC, a true 3-d stack.
But many technical questions ( ideal materials set & process flow, yield, device perf., reliability ) that still need to be settled re: 3-d w/ TSVs.
If it clicks for SMIC then success in developing and implementing TSV technology will be game changing success for them, as further acceptance of 3D manufacturing of silicon is totally dependent of the success of TSV.
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