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Re: Battle of 3D ICs
chipmonk0   10/22/2013 11:04:38 AM
@Rick :

I wonder if TSMC is now doing REAL 3-d stack ( i,e. TSVs in active dice and stacking them ) or still just 2.5-d ( NO TSVs in the active dice, no active die on top of another ) like their earlier Vertex modules for Xilinx.

Your point about difficulty is however well taken. It took Micron at least 2 years to start sampling their HMC, a true 3-d stack.

But many technical questions ( ideal materials set & process flow, yield, device perf., reliability ) that still need to be settled re: 3-d w/ TSVs.

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TSV is a very promising technology for 3D
Kinnar   10/22/2013 4:18:10 AM
If it clicks for SMIC then success in developing and implementing TSV technology will be game changing success for them, as further acceptance of 3D manufacturing of silicon is totally dependent of the success of TSV.

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Re: Battle of 3D ICs
junko.yoshida   10/21/2013 11:41:25 PM
Rick, that's definitely a good data point.

rick merritt
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Re: Battle of 3D ICs
rick merritt   10/21/2013 11:37:46 PM
Interesting the SMIC news comes the same day TSMC announced it was finally in volume production of Xilinx 2.5-D FPGAs. TSMC was early here and it seems the tech is harder than anyone thought.

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Battle of 3D ICs
junko.yoshida   10/21/2013 10:42:18 PM
What's clear from SMIC's announcement today is the emerging battle -- over who gets more market share -- in the 3D IC foundry business.

Do you see any foundries doing better than others when it comes to producing TSV technology-based stacked devices?

As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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