The vertical nanowire width has to include silicon body (channel), 2x gate oxide thickness, and 2x gate thickness. So 40 nm is no surprise. Maybe this width defines a pitch, or a new feature dimension defines the node.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.