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rick merritt
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Welcome back, Brian!
rick merritt   10/23/2013 12:13:35 AM
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Good to see your face and prose in eet.com!

AnySilicon
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Freelancer
Welcome back home!
AnySilicon   10/23/2013 8:39:44 AM
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Welcome back home!

David Ashton
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Blogger
Good to see you back
David Ashton   10/24/2013 3:29:51 PM
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It is great to see you back here again Brian, even if you are talking waaay over my head.  I hope I can make it to DW/EEL 14 and we can catch up over a beer....

Brian Fuller2
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Re: Good to see you back
Brian Fuller2   10/24/2013 7:10:55 PM
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David, just "a" beer? 

;   )

David Ashton
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Re: Good to see you back
David Ashton   10/24/2013 7:30:13 PM
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@Brian.....Or 17.....

Brian Fuller2
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Blogger
Re: Good to see you back
Brian Fuller2   10/24/2013 7:31:22 PM
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Yikes. Somewhere in between, methinks! Either that or you're carrying me out!

David Ashton
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Blogger
Re: Good to see you back
David Ashton   10/24/2013 8:26:52 PM
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@Brian....you're not going to let a Zimbabwean drink you under the table, surely??   Anyway, I won't be driving.... :-)

Frank Eory
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CEO
Not every IC is a huge SoC
Frank Eory   10/25/2013 1:23:40 PM
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Mr. Sanguinetti's comments about tool chain complexity are spot-on if one accepts the premise that EDA tools must move to a higher level of abstraction for design and also for verification. While this premise may be true for large SoC's, let's not forget that not all ICs are large SoCs. Many designs being taped out today don't use High Level Synthesis, for example, and not every design requires a verification flow based on System Verilog.

KarlS01
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Manager
Re: Not every IC is a huge SoC
KarlS01   11/3/2013 11:44:49 AM
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The non-SoC designs seem to be neglected because of all the SoC HLS hype.

Another thing is that many designers want vendor/device independence and avoid even using IP and infer everything in HDL. 

If true dual port memory blocks were available across the board, then using one ram for sequencing/control and another for data variables would allow C syntax for source code and for modeling the function by a C#/C++ OOP model using the same heirarchy and structure as the hardware.

The memory access and cycle times are fast enough to match designs using regs and muxes in many cases.

Still another programming language is not necessarily the right answer.  More ways to use block memory should be explored.



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