Mr. Sanguinetti's comments about tool chain complexity are spot-on if one accepts the premise that EDA tools must move to a higher level of abstraction for design and also for verification. While this premise may be true for large SoC's, let's not forget that not all ICs are large SoCs. Many designs being taped out today don't use High Level Synthesis, for example, and not every design requires a verification flow based on System Verilog.
The non-SoC designs seem to be neglected because of all the SoC HLS hype.
Another thing is that many designers want vendor/device independence and avoid even using IP and infer everything in HDL.
If true dual port memory blocks were available across the board, then using one ram for sequencing/control and another for data variables would allow C syntax for source code and for modeling the function by a C#/C++ OOP model using the same heirarchy and structure as the hardware.
The memory access and cycle times are fast enough to match designs using regs and muxes in many cases.
Still another programming language is not necessarily the right answer. More ways to use block memory should be explored.