1/ TFT is quite different from 3D SONOS because in a planar device (esp large ones like TFT) you can easily go to larger grain size (the main parameter that determines the read current). In 3D memory it is definitely much more challenging.
2/ It is indeed not easy to fully recrystallize the channel, but in our case we were capable of doing this down to 300nm, which is of the order of the needed channel dimensions (~1um). There are, however, other ways to limit the channel depth which make the technique more applicable.
with complex semiconductor processes and relatively larger number of process steps, the 3D integration is challenging. Local annealing can only be a temporary solution as the buried layers will not be cured. We need either better material or dedicated heat conducting channels for energy transport.
The effect of the disorder in the channel material of the MOS devices on conduction properties is well known. For instance, we did a study when at Matrix Semiconductor on this and it was published in the IEEE TED in 2004 ("On the conduction mechanism in polycrystalline silicon thin-film transistors", IEEE TED Nov., 2004). In general, the engineering approach considers the grain boundaries as effective barriers to conduction of the carriers (electrons in this case). The physicists consider the states in the bandgap as the cause of poor conduction. The more states, the more difficult it is to invert a channel in the MOS device and the resultant charged states act as mobility inhibitors. The main point is, the less disorder the closer is the conduction to monocrystalline silicon. Therefore, techniques that reduce disorder work well (such as laser annealing which is fairly standard in the flat panel TFT world). The quote from the above paper is the general summary:
"This study shows the physics of polycrystalline silicon TFT conduction to be of the same form as amorphous and single crystal devices with the degree of disorder as the sliding scale between the two extremes."
It is the first time, I see a comparison of Poly-Si to Amorphous Poly (as deposited) and not to pure silicon. As a result a 10 time improvement is really easily achievable. The next decade (crystal Si) of improvement will be much more challenging. Notice than Laser annealing is a common process that is already used in production for most (planar) TFT device. So I do not see the originality here.
Specially as say Resistion, It will be hard to apply it to 3D memory as this is a surface technique.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.