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vanhoudt
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3D memory
vanhoudt   10/29/2013 5:52:13 AM
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few remarks to be added:

1/ TFT is quite different from 3D SONOS because in a planar device (esp large ones like TFT) you can easily go to larger grain size (the main parameter that determines the read current). In 3D memory it is definitely much more challenging.

2/ It is indeed not easy to fully recrystallize the channel, but in our case we were capable of doing this down to 300nm, which is of the order of the needed channel dimensions (~1um). There are, however, other ways to limit the channel depth which make the technique more applicable.

 

wilber_xbox
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Re: 10x
wilber_xbox   10/26/2013 12:22:13 PM
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with complex semiconductor processes and relatively larger number of process steps, the 3D integration is challenging. Local annealing can only be a temporary solution as the buried layers will not be cured. We need either better material or dedicated heat conducting channels for energy transport.

toom_tabard
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Re: 10x
toom_tabard   10/25/2013 11:10:01 PM
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The effect of the disorder in the channel material of the MOS devices on conduction properties is well known. For instance, we did a study when at Matrix Semiconductor on this and it was published in the IEEE TED in 2004 ("On the conduction mechanism in polycrystalline silicon thin-film transistors", IEEE TED Nov., 2004). In general, the engineering approach considers the grain boundaries as effective barriers to conduction of the carriers (electrons in this case). The physicists consider the states in the bandgap as the cause of poor conduction. The more states, the more difficult it is to invert a channel in the MOS device and the resultant charged states act as mobility inhibitors. The main point is, the less disorder the closer is the conduction to monocrystalline silicon. Therefore, techniques that reduce disorder work well (such as laser annealing which is fairly standard in the flat panel TFT world). The quote from the above paper is the general summary:

"This study shows the physics of polycrystalline silicon TFT conduction to be of the same form as amorphous and single crystal devices with the degree of disorder as the sliding scale between the two extremes."

etienneazerty
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Re: 10x
etienneazerty   10/25/2013 8:45:29 PM
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Amorphous Si is not a crystal as a result the electron mean free path is very short and defect level is high inducing a very bad semiconductor (Nobody use as deposited Poly for transport)

As a result you have to heat it in order to organized it into a crystal. (Think of how to create wafer). However there is a whole range of Poly-Si quality between amorphous and pure Silicon. 

The effective mobility between a-Si and c-Si is almost 3 decades.

 

krisi
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Re: 10x
krisi   10/25/2013 10:26:08 AM
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thank you @etiennazerty "As a result a 10 time improvement is really easily achievable"...why? what is physically different between poly and amorphous to give 10x improvements?


etienneazerty
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Re: 10x
etienneazerty   10/25/2013 6:31:06 AM
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It is the first time, I see a comparison of Poly-Si to Amorphous Poly (as deposited) and not to pure silicon. As a result a 10 time improvement is really easily achievable. The next decade (crystal Si) of improvement will be much more challenging.
Notice than Laser annealing is a common process that is already used in production for most (planar) TFT device. So I do not see the originality here.

Specially as say Resistion, It will be hard to apply it to 3D memory as this is a surface technique.

rick merritt
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Good report, Janine!
rick merritt   10/24/2013 1:55:16 PM
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Imec and others are idoing interesting wotrk in chip stacks, too.

resistion
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CEO
top-down variation
resistion   10/24/2013 10:25:43 AM
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Gets me thinking about top to bottom variation especially for taller structures.

krisi
User Rank
CEO
10x
krisi   10/23/2013 5:01:01 PM
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10 times higher reading current? how is that physically possible?



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