Being an FPGA, it is really tiny!! It is ideal for the applications for which it is made: consumes extremely low power and "... only wakes the application processor when the occasion demands".
What about storing the configuration? Does it need a FLASH or some memory to store the configuration and picks it during power-up like the traditional FPGAs? Why there was an FPGA needed in this size, where the functions it might do for sensing application, could be done by a tiny CPLD?
Yep app processors need to stay off as much as possible. We will need a multi-level 'cache' equivalent for sensor functions. Need to have levels of processing available for different functions each at 1/10 the power of the previous. The lattice parts are one piece of the puzzle.
It seems that many programmable logic devices are starting to enable always-on sensor solutions. This is a need for a plethora of new mobile applications -- I just wonder if SoC switching time rates from low power modes to active run will be able to take advantage of this capabilities without drawing the battery charge saved by sensor frontend!!
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.