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R_Colin_Johnson
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R_Colin_Johnson   10/30/2013 11:56:34 PM
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With stacked memory, heat is not as much of an issue, since individual memory locations are accessed only occasionally. But for other types of chips, like processors, the ALUs, for instance, are constantly running making for hot spots that need to be cooled if they are inside the stack.

daleste
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daleste   10/30/2013 11:29:59 PM
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WOW, liquid cooling for multichip modules.  I guess at some point, heat has to be addressed.

R_Colin_Johnson
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R_Colin_Johnson   10/30/2013 1:06:31 PM
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Micron and IBM both are using chip stacks connected by through silicon vias (TSVs) and IBM is using microfluidics to run water between the chips to cool them!

wilber_xbox
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wilber_xbox   10/30/2013 11:19:45 AM
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there are not a lot of alternatives for 3D stack. I hear that Micron and IBM are working on such a technology. I do not know how the SK Hynix technology is different from the one developed by Micron.

R_Colin_Johnson
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Re: another alternative
R_Colin_Johnson   10/29/2013 3:49:43 PM
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One big advantage of BeSang's approach is that its 3-D layers are very thin--less than 0.5 microns--which allows them to use high-density conventional vias, compared to die stacking which requires lower density through-silicon vias.

Regarding whether it will work, SK Hynix has been evaluating BeSang's technology for quite some time, so they--at least--have confidence it will work.

resistion
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another alternative
resistion   10/29/2013 3:36:07 PM
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Interesting response to HMC, assuming the low temperature vertical transistors work as desired.

R_Colin_Johnson
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R_Colin_Johnson   10/29/2013 1:21:30 PM
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BeSang claims its approach will enable 3-D memory to be stacked on any type of CMOS chip--not just DRAM--so I expect others to license it soon, now that SK Hynix has taken the plunge. 

wilber_xbox
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wilber_xbox   10/29/2013 1:11:42 PM
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Thanks Collin for explanation on the 3D memory stack. After hitting the wall in 2D, the natural choice for more memory in the same area is to stack layers.



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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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