If you go back and look at my comments last Friday ( Nov 1 ) to your blog on the ChipWorks Teardown of the iPad Air you will notice the same things you heard from the Panelist at IWLPC earlier this week.
re: the physical arrangement of Memory and SoC while iPhones and all other Smart Phones & Tablets have pretty much stuck to the PoP package, we do see several mutations in successive generations of the iPad.
The iPad started off with a PoP package, but in the iPad 2 as the no. of GPUs in the SoC ( still 45 nm non HKMG CMOS ) had to grow to cater to the higher res. Retina for the large screen the thermal load went up. The thermal path on the top of the SoC could no longer be blocked by the DRAM in PoP configuration, it had to be pulled off and a Heat sink had to be slapped on in its place. The DRAM moved to the other side of the Motherboard under the shadow of the SoC package - a direct interconnect through the vias in the Motherboard, only not quite as low in parasitics as in a true TSV, hence the "poor mans.." remark that you heard at the IWLPC.
On the downside the Double sided Motherboard prevented the iPad from getting any slimmer.
To make the slimmer iPad Air possible the Double sided MB had to be chucked in favor of a virtually single sided MB ! The DRAMs are now on the same side of the MB as the A7 - right next to it. Traces thru the MB are longer than in earlier arrangements ( PoP,.. ) and once again their parasitics enter into the calculation of Timing Margins, Bandwidth, Power etc.
The A7 now has the benefit of Samsung's best ( 28 nm with HKMG transistors, low leakage, lower voltage) but that Heat sink is still on it ! Those were some of the things I was alluding to in my comment of Nov 1.
@Any Silicon: I did not note in the story that Abe Yee of Nvidia said his opinion is the kind of turnkey one-stop-shop TSMC is offering in chip stacks is very attractive.
While competition lowers prices, he suggested it will be very difficult and costly for a supply chain of as many as 16 combinations of fabs and packaging houses to get in synch to offer something competitive.
@ Chipmonk: Over email I invited Richard Yee of Samsung, one of the people at the ARM Tech Con booth, to answer your question about the demo. Good question and I appreciate your observations.
Just to clarify, the person at the panel was saying the pcb between the memory chip (I guess the PoP you reference) and the A7 on the other side of the board was surprsingly simple (6 layers total). The combo of the A7, simple pcb and memory stack on the other side of the board was what he referred to as a "poor man's 3-D IC."
Very imsightful comments @chipmonk0...would you be interested in giving a talk on this topic at CMOS emerging technologies symposium in Grenoble in 2014? preliminary program at www.cmosetr.com, firstname.lastname@example.org
that "poor man's 3D IC " you heard about at the IWLPC workshop was none other than the lowly PoP package I had commented on re: your blog last week on ChipWorks teardown of the new iPad Air. For at least the last 3 years the PoP package has been ubiquitous in all Smart Phones and many Tablets ( though not in iPads anymore ).
re: 3D IC with TSVs you could look up my comments in EE Times following SemiCon West ( where I had given a 1 hr long invited talk on it ) back in July. As someone who was very involved in developing the Adv. Packaging technologies now considered critical to Smart Phones etc., IMHO that the mainstream effort for 3-d w/ TSVs has been sub - par when it comes to giving enough attention to the basic Science and not sufficiently result oriented ( too big a role of newbie W. European Labs with socialized money ), hence the delay / high cost.
However not all 3D - stacking in the Wide I/O format require TSVs e,g. if you stick just one DRAM face down on top of a SoC. If that single DRAM has enough Bytes then TSVs and all the associated pain can be avoided. Such stacks have been built, the energy for data xfer at a 2x higher Bandwidth has been measured to be just a quarter of that for PoP.
This could very well be the "low pain" replacement for good ole PoP as LP DDR size goes beyond 8Gb per chip.
From your Slide Show report of Nov 4 on ARM Tech Con I see that Samsung was claiming very similar improvements by combining their Exynos Octa to Wide I/O RAM. Unfortunately I missed the TechCon Exhibition as it had not yet opened on Tuesday Oct 29 when I had my paper there. Wonder if Samsung too was using a single Wide I/O DRAM face down. And how bout the Clock Rate and Bandwidth ?
Appreciate if you can get back to your contacts at Sam and do a little poking around.
The real win is with the other type of 3D IC - the monolithic 3D. Samsung is already in massproduction with their 3D NAND and others are about to join. And we are now seeing good progress with monolithic 3D IC for logic as well. While dimensional scaling was for many years the best path to increase device functionaly or reduce device cost it is not anymore. The industry path forward now is monolithic 3D.
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