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AnySilicon
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TSMC is going to smash assembly house
AnySilicon   11/8/2013 7:00:01 AM
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TSMC is also playing a role in this market and already olanning to take a big bite in the ASAT market. My take here: http://anysilicon.com/tsmc-going-smash-packaging-houses/

Or_Bach
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Re: TSMC is going to smash assembly house
Or_Bach   11/8/2013 9:06:38 AM
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The real win is with the other type of 3D IC - the monolithic 3D. Samsung is already in massproduction with their 3D NAND and others are about to join. And we are now seeing good progress with monolithic 3D IC for logic as well. While dimensional scaling was for many years the best path to increase device functionaly or reduce device cost it is not anymore. The industry path forward now is monolithic 3D.

chipmonk0
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CEO
Poor man's 3D IC for Apple A7 ...
chipmonk0   11/8/2013 11:54:02 AM
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@ Rick :

that "poor man's 3D IC " you heard about at the IWLPC workshop was none other than the lowly PoP package I had commented on re: your blog last week on ChipWorks teardown of the new iPad Air. For at least the last 3 years the PoP package has been ubiquitous in all Smart Phones and many Tablets ( though not in iPads anymore ).

re: 3D IC with TSVs you could look up my comments in EE Times following SemiCon West ( where I had given a 1 hr long invited talk on it ) back in July. As someone who was very involved in developing the Adv. Packaging technologies now considered critical to Smart Phones etc., IMHO that the mainstream effort for 3-d w/ TSVs has been sub - par when it comes to giving enough attention to the basic Science and not sufficiently result oriented ( too big a role of newbie W. European Labs with socialized money ), hence the delay / high cost.

However not all 3D - stacking in the Wide I/O format require TSVs e,g. if you stick just one DRAM face down on top of a SoC. If that single DRAM has enough Bytes then TSVs and all the associated pain can be avoided. Such stacks have been built, the energy for data xfer at a 2x higher Bandwidth has been measured to be just a quarter of that for PoP.

This could very well be the "low pain" replacement for good ole PoP as LP DDR size goes beyond 8Gb per chip.

From your Slide Show report of Nov 4 on ARM Tech Con I see that Samsung was claiming very similar improvements by combining their Exynos Octa to Wide I/O RAM.  Unfortunately I missed the TechCon Exhibition as it had not yet opened on Tuesday Oct 29 when I had my paper there. Wonder if Samsung too was using a single Wide I/O DRAM face down. And how bout the Clock Rate and Bandwidth ?

Appreciate if you can get back to your contacts at Sam and do a little poking around.

krisi
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CEO
Re: Poor man's 3D IC for Apple A7 ...
krisi   11/8/2013 12:55:19 PM
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Very imsightful comments @chipmonk0...would you be interested in giving a talk on this topic at CMOS emerging technologies symposium in Grenoble in 2014? preliminary program at www.cmosetr.com, kris.iniewski@gmail.com

rick merritt
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Re: Poor man's 3D IC for Apple A7 ...
rick merritt   11/8/2013 1:23:56 PM
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@ Chipmonk: Over email I invited Richard Yee of Samsung, one of the people at the ARM Tech Con booth, to answer your question about the demo. Good question and I appreciate your observations.

Just to clarify, the person at the panel was saying the pcb between the memory chip (I guess the PoP you reference) and the A7 on the other side of the board was surprsingly simple (6 layers total). The combo of the A7, simple pcb and memory stack on the other side of the board was what he referred to as a "poor man's 3-D IC."

chipmonk0
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CEO
Re: Poor man's 3D IC for Apple A7 ...
chipmonk0   11/8/2013 1:26:00 PM
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Gracias !

 

chipmonk0
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CEO
Re: Poor man's 3D IC for Apple A7 ...
chipmonk0   11/8/2013 2:05:41 PM
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@ Rick

If you go back and look at my comments last Friday ( Nov 1 ) to your blog on the ChipWorks Teardown of the iPad Air you will notice the same things you heard from the Panelist at IWLPC earlier this week.

re: the physical arrangement of Memory and SoC while iPhones and all other Smart Phones & Tablets have pretty much stuck to the PoP package, we do see several mutations in successive generations of the iPad.

The iPad started off with a PoP package, but in the iPad 2 as the no. of GPUs in the SoC ( still 45 nm non HKMG CMOS ) had to grow to cater to the higher res. Retina for the large screen the thermal load went up. The thermal path on the top of the SoC could no longer be blocked by the DRAM in PoP configuration, it had to be pulled off and a Heat sink had to be slapped on in its place. The DRAM moved to the other side of the Motherboard under the shadow of the SoC package - a direct interconnect through the vias in the Motherboard, only not quite as low in parasitics as in a true TSV, hence the "poor mans.." remark that you heard at the IWLPC. 

On the downside the Double sided Motherboard prevented the iPad from getting any slimmer.

To make the slimmer iPad Air possible the Double sided MB had to be chucked in favor of a virtually single sided MB ! The DRAMs are now on the same side of the MB as the A7 - right next to it. Traces thru the MB are longer than in earlier arrangements ( PoP,.. ) and once again their parasitics enter into the calculation of Timing Margins, Bandwidth, Power etc. 

The A7 now has the benefit of Samsung's best ( 28 nm with HKMG transistors, low leakage, lower voltage) but that Heat sink is still on it ! Those were some of the things I was alluding to in my comment of Nov 1.

rick merritt
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Re: Poor man's 3D IC for Apple A7 ...
rick merritt   11/8/2013 3:37:34 PM
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@Chipmonk: Great perspective! I'd love to read YOUR teardowns of these iProducts

chipmonk0
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CEO
Re: Poor man's 3D IC for Apple A7 ...
chipmonk0   11/8/2013 5:38:50 PM
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you could look up my hour long rant and rave at ARM TechCon last week, just skip the Math.

chipmonk0
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CEO
Dick James & ChipWorks
chipmonk0   11/8/2013 5:48:41 PM
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have been a valuable resource over the years. They were indeed the first to report SONY using face to face SoC - DRAM in wide I/O in their handheld Vita game system.

They ought to branch out into analyzing Packages as well, since integration at the Package level looks ever more attractive as chasing Moore's Law becomes unaffordable for most.

Dick James
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Manager
Re: Poor man's 3D IC for Apple A7 ...
Dick James   11/8/2013 3:09:29 PM
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Hi Guys,

Sony has been using Samsung wide i/o DRAM in a face-to-face stack in the PS Vita for almost two years now. I hesitate to push my own blog, but it's decribed here:

http://chipworksrealchips.blogspot.ca/2012/07/sonys-ps-vita-uses-chip-on-chip-sip-3d.html

 

rick merritt
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Author
Re: Poor man's 3D IC for Apple A7 ...
rick merritt   11/8/2013 3:36:41 PM
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@Dick: Thanks, I didn't think anyone was using Wide IO

Or_Bach
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Rookie
Re: Poor man's 3D IC for Apple A7 ...
Or_Bach   11/8/2013 10:38:15 PM
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Hi Rick

Yes, monolithic 3D provide the highest bandwidth between memory and logic, as the connection to the memory is extremly short - less than 1 micron. 

chipmonk0
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CEO
Re: Poor man's 3D IC for Apple A7 ...
chipmonk0   11/9/2013 11:38:04 AM
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@ Zvi Or Bach :

 

has any monolithic 3D chip with Logic on top of memory stack been built yet ? Quite aside from the process integration issues would n't the difference in floorplan between Memory and a SoC increase the interconnect length, thus largely negating the advantage of short vias ?

rick merritt
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Author
Re: Poor man's 3D IC for Apple A7 ...
rick merritt   11/10/2013 1:11:24 AM
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@Zvi: Can you describe a memory+logic design done in your approach?

Or_Bach
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Re: Poor man's 3D IC for Apple A7 ...
Or_Bach   11/10/2013 3:53:09 AM
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Hi Rick

Quoting from the Tip Sheet for 2013 IEDM:

"The monolithic 3D architecture demonstrated high performance – 3-ps logic circuits, 1-T 500ns nonvolatile memories and 6T SRAMs with low noise and small footprints, making it potentially suitable for compact, energy-efficient mobile products. (Paper #9.3, "Monolithic 3D Chip Integrated with 500ns NVM, 3ps Logic Circuits and SRAM," C–H. Shen et al, National Nano Device Laboratories)

rick merritt
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Author
Re: TSMC is going to smash assembly house
rick merritt   11/8/2013 1:25:29 PM
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Hi Zvi; Does your approach address the issue of getting higher bandwidth between the memory and logic (processor and RAM)?

rick merritt
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Author
Re: TSMC is going to smash assembly house
rick merritt   11/8/2013 1:28:22 PM
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@Any Silicon: I did not note in the story that Abe Yee of Nvidia said his opinion is the kind of turnkey one-stop-shop TSMC is offering in chip stacks is very attractive.

While competition lowers prices, he suggested it will be very difficult and costly for a supply chain of as many as 16 combinations of fabs and packaging houses to get in synch to offer something competitive.

 

_hm
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CEO
Yield and Design for Test
_hm   11/9/2013 7:47:26 AM
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Apple's approach to poor man's 3D packaging must have logic behind it. Two of that can be very good yield for current manufacturing and Design for Testability. If you need to meet these two aspects, Apple's approach may be prudent.

Real 3D packagin may be more essential for wearable technology and devices.

 

genegoebel
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Mass production
genegoebel   11/11/2013 12:55:19 PM
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The reality is simple. Its been mentioned numerous times throughout prior comments. Simply put we need the volume equivalent to current MCU or DRAM. Volume will make 3-D affordable. So when there is demand for 200,000 WPM we will see mass adoption.

genegoebel
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Mass production
genegoebel   11/11/2013 12:55:21 PM
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The reality is simple. Its been mentioned numerous times throughout prior comments. Simply put we need the volume equivalent to current MCU or DRAM. Volume will make 3-D affordable. So when there is demand for 200,000 WPM we will see mass adoption.



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