The "six things" are a quite good summary, and they certainly seem to apply. BUT the really critical thing is for the board designer to be able to understand the signals on every element. Design rules are quite handy, and probably they are the only means for automated checking, but they are not really an adequate substitute for understanding every signal and how it woulod interact with the signals that couple to that trace from adjacent traces. So either the designer needs to have a lot of insight and understanding or the individual who designed the circuit must be able to tag each connection with the characteristics of the signal. Of Course that gets to be huge for a complex board, but the effort may be worth the cost if the system functions perfectly on the very first layout. Not just adequately, but perfectly.
You are correct there must be a close relationship between the PCB designer and the designer of the circuit.
In the past I have acheived this in several ways
1) Generating the correct net class constraints which can be applid to the types of nets e.g. power, return, 50 Ohm impedance, 100 Ohm impedance. You can define a number of rules for each type then hhow close they can be to each other etc. You can also define the special analogue and digital types for mixed signal boards to ensure correct seperation.
2) Define differential pairs in the schematic - many tools allow you to put attributes on signas to show they form part of a differential pair.
3) Define signal groups which must have the same electrical length, this is very important for applications like memories, parallel interfaces etc.
4) A formal layout constraints document produced by the schematic designer providing guidance for the PCB layout engineer. This can inlcude things like identification of currents on the power rails, acceptable voltage drops. suggested floor plan of the components and so on. This does not mean the designer and PCB engineer will not need to talk frequently but it does formalise the transfer of information.
5) Define the PCB stack - and check the track widths and spacing are acceptbale with the PCB vendor to produce the board with a acceptable yield.
@Adam: In addition to the six point you have described, I would add another one that has driven me nuts more often I would wish to: design for EMC/EMI.
I still remember a product for which I developed the PCB and that was a real pain in the ass. The thing included a MP3 player and a GPS module -- it was a kind of outdoor audioguide. The On-Chip audio output was implemented by using a sigma-delta modulation, and it took me tons of hours to filter the "carrier" higher frequencies and addapt the delivered current before the audio stream EMI stopped shooting down the GPS system.
Additional comments on designing a multi-layer high speed printed circuit board
*Stack up is essential to design up front based on the input requirements especially for high speed designs. Design decisions on the stack up material and its dielectric constant, the distribution of power planes and digital planes, ground-power-power-ground method can be utilized to save on the # of layers. If the sensitive and critical high speed digital signals are not micro-strip routed then they should be routed on layers close to the component with blind vias to reduce via inductance.
*In desigining vias, pre-layout and post-layout via simulations utilizing HFSS Ansys toolkits can be conducted. The results of these simulations can be utilized to make decisions on whether sequential laminations on the stackup are required.
*Post-layout simulations can be conducted utilizing Allegro editor, momentum and time domain PCIe channel simulators within advanced design systems. The results of these simulations can be utilized to make design decisions related to constraint manager inputs such has maximum trace lengths, the impact of vias, different types of stack up materials, micro strip routing versus stripline routing, impact of nearby traces and vias for stripline routing.
*For high speed designs, the on-board bypass capacitor placement for FPGAs and DDR3 memory integrated chips, the post layout power plane shapes, the resonance peaks and cross overs on the impedance curves can be analyzed by utilizing power integrity simulations within the Cadence sigrity toolkit.
*Constant communication is also required between the hardware design engineer and the pcb designer, especially when requirements change example, modifications are made to the schematic, timing parameters on constraint manager hence needs modification and then the design needs to re-synced.
Replay available now: A handful of emerging network technologies are competing to be the preferred wide-area connection for the Internet of Things. All claim lower costs and power use than cellular but none have wide deployment yet. Listen in as proponents of leading contenders make their case to be the metro or national IoT network of the future. Rick Merritt, EE Times Silicon Valley Bureau Chief, moderators this discussion. Join in and ask his guests questions.