Just stumbled over this on twitter (#FPGA) - making use of this right now.
I resolved the conflict a cruder way - the addresses are compared, and if they match then the datain is registered to place on the dataout of the other port, and the enable of the read port is inhibited (don't know if I explained that correctly or not!).
This was discussed briefly on the Programmable Planet a couple months back, in the context of building a [1W+2R] memory from the "simple dual port" [1W+1R] block RAMs that are available in the Lattice ICE40 family.
I would post a direct link, unfortunately the Programmable Planet was recently destroyed by the UBM division of the Vogon Constructor Fleet in order to make way for a new subspace billboard.
As of the moment, Google has a cached copy of the thread here:
@Brian: This is not the same as using 2 simple dual ports. There both RAMs must be written every time to maintain integrity.
In this case is special because true dual port can write one port and read a different address simultaneously on the other port. The write to the second port is a write thru only if the addresses are the same.
Therewfore I think there is no way to make a true dual port using 2 simple dual ports because for writes both addresses have to be the same.
@Alvie "This is the first part of the artice. The second part will deal with adding an extra write port to the design"
Hopefully I haven't disrupted the natural order of the blog series in replying to Karl's post ( which I might have misunderstood anyway ).
Perhaps not obvious from my original post here, but the intent of the earlier APP link was to cover some practical issues ( synthesis directives & coding styles ) needed to successfully infer a "replicated" multiport structure with Synplify in an FPGA target having only Simple Dual Port RAM.