From a stictly designer perspective, yes, I think FD SOI has advantages because it allows the freedom and flexibility of a planar or 2d process. This is especially attractive to analog designers who are looking to create very custom devices and optimize for timing, frequency, noise, etc.
Well, with everything else, FinFET technologies will have to stand the test of time to see if it can reduce costs, if it is reliable, and if it can support the many devices that are on the market. If it can, the learning curve for FinFET technologies will not be a problem for designers.
FinFETs just quantize the size of transistors and to make them manufactureable the fin pitch and poly pitch need to be pretty much fixed.
The thing I think the foundaries are missing is planar devices for analog circuits that do not translate well to FinFET. They should be able to do it the same way traditional CMOS processes can have bipolar devices. While die area for planar circuits would be bigger, it would make the process more flexible and give designers a stepping stone between planar processes and full FinFET design.
I love the graphic renderings of these FinFETs. Has anyone seen a resource that shows these next to a traditional 2D design, complete with explanation of how electrons flow in both designs? That way a non-device designer can see exactly what it is that makes these FinFETs advantageous?
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.