This is a very interesting column, Max. Your explanation about the physical processes involved in building this kind of 3D ICs is very clear and enlightening.
But I've a question for you. One of the main issues with 3D ICs is how to get rid of the extra heat that is produced inside the "dice". I've heard that a very promising alternative is embedding active cooling devices into the IC -- e.g. Peltier towers. Do you have any clue about this?
@Garcia: One of the main issues with 3D ICs is how to get rid of the extra heat that is produced inside the "dice". I've heard that a very promising alternative is embedding active cooling devices into the IC -- e.g. Peltier towers. Do you have any clue about this?
Sadly not -- but I'm sure the folks at MonolithicIC3D do. I will "ping" them and ask them to comment here.
Heat removal is a known issue and important one. The advantage of the monolithic 3D stacked device is that all upper layers are thin and not too far from the base wafer bulk or from the upper surface of the device. In IEDM 2012 we had published joint work with Stanford University showing that the heat could be very effectively be removed using the power distribution network (PDN). The work was also covered by a follow on blog: http://www.monolithic3d.com/2/post/2012/12/can-heat-be-removed-from-3d-ic-stacks.html
Or_Bach: "the heat could be very effectively be removed using the power distribution network (PDN)"
Thank you very much for this valious update. The blog you are pointing out is really interesting. So, you reuse the Power Distribution Network in the same way some heat sinks use heat pipes -- but immersed into the "dice". Is this right?
Yes, copper is a good heat conductor and there is a general need to have a good power delivery which imply use of thick copper wires across the device with many vias to spread the power across the device.
In monolithic 3D we can have many vias which provides good heat transfer from the inner transistors layers to the device heat-sink. And the very thin layers of monolithic 3D means that the distance from where the heat is being generated to where it could dissipate is only few microns. Accordingly the power-distribution-network could be used to effectively removed the inner heat.
It should be noted that monolithic 3D is most effective way to reduce the overall heat generated in IC device as it significantly reduce the average interconnect length.
There seems to be some usual confusion going on here between 3-d stacking of dice ea. first processed separately on separate wafers to build device ( the original question by Lasheras ) and devices built one on top of another on the same wafer ( in the response by Zvi ).
in the first case the thermally conductive Cu used to fill the through vias can aid vertical heat dispersal but not completely since they also introduce stress if placed too close to the transistors. the TSVs do nothing to directly aid lateral heat dispersal. IBM / 3M and a few others are working on this part as local heat build up impacts memory refresh times.
For the second config. of 3-d, which Zvi has been championing for a while, what are the vias between transistors built one on top of another made of ? Copper or still much less conductive Tungsten ? Samsung's 3-d NAND sticks to usual CVD W. But as Zvi says, the heat transfer distances are within microns and so the fluxes could be acceptable even with vias filled with CVD W which has a k just a quarter of Cu.