Breaking News
Comments
Newest First | Oldest First | Threaded View
Max The Magnificent
User Rank
Blogger
Re: how many gates?
Max The Magnificent   12/6/2013 12:48:34 PM
NO RATINGS
@DrFPGA: ...we know you never exagerate...

I've told you a million times that I don't exagerate LOL. Does anyone still talk about "system gates" -- if so, I can certainly tie all these things together -- I learned all sorts of cool stuff last .... eeek, I can't talk about that yet...

DrFPGA
User Rank
Blogger
Re: how many gates?
DrFPGA   12/6/2013 12:44:24 PM
NO RATINGS
I guess this means you are going to finally provide the correct conversion from gates to system gates to 4 input LUTs, etc? All will be revealed is a big promise Max, and we know you never exagerate...

sgabriel
User Rank
Rookie
Re: how many gates?
sgabriel   12/3/2013 8:13:47 PM
NO RATINGS
@krisi, that comes out to be >5 billion CMOS transistors in Arria 10. Very impressive for mid-range FPGA, to say the least.

krisi
User Rank
CEO
Re: how many gates?
krisi   12/3/2013 7:32:05 PM
NO RATINGS
thank you @sgabriel...over 1M logic elements, impressive...how many CMOS transistor is that?

sgabriel
User Rank
Rookie
Re: how many gates?
sgabriel   12/3/2013 7:03:38 PM
NO RATINGS
@krisi, Altera has disclosed product details of our 20nm Arria 10 family. The largest Arria 10 device has up to 1.15M logic elements, integrated into a mid-range device. And public software support is available today. http://www.altera.com/devices/fpga/arria-fpgas/arria10/arr10-index.jsp

Max The Magnificent
User Rank
Blogger
Re: how many gates?
Max The Magnificent   12/3/2013 3:51:44 PM
NO RATINGS
@Kris: ...sounds mysterious Max...

Just call me "Max, Man of Mystery" LOL

krisi
User Rank
CEO
Re: how many gates?
krisi   12/3/2013 3:42:50 PM
NO RATINGS
sounds mysterious Max...looking forward

Max The Magnificent
User Rank
Blogger
Re: how many gates?
Max The Magnificent   12/3/2013 3:34:23 PM
NO RATINGS
@Kris: How many gates Xilinx can pack in 20nm process?

I know, but I'm not allowed to tell you just at the moment. All I can say is to keep on visiting Programmable Logic Designline because all will soon be revealed...

krisi
User Rank
CEO
how many gates?
krisi   12/2/2013 4:27:23 PM
NO RATINGS
How many gates Xilinx can pack in 20nm process? Kris



EE Life
Frankenstein's Fix, Teardowns, Sideshows, Design Contests, Reader Content & More
Max Maxfield

Dr. Duino Diagnostic Shield Deduces Dilemmas in Arduino Shield Stacks
Max Maxfield
13 comments
As you are probably aware, I'm spending a lot of my free time creating Arduino-based projects, such as my Inamorata Prognostication Engine, my BADASS Display, and my Vetinari Clock.

EDN Staff

11 Summer Vacation Spots for Engineers
EDN Staff
20 comments
This collection of places from technology history, museums, and modern marvels is a roadmap for an engineering adventure that will take you around the world. Here are just a few spots ...

Glen Chenier

Engineers Solve Analog/Digital Problem, Invent Creative Expletives
Glen Chenier
15 comments
- An analog engineer and a digital engineer join forces, use their respective skills, and pull a few bunnies out of a hat to troubleshoot a system with which they are completely ...

Larry Desjardin

Engineers Should Study Finance: 5 Reasons Why
Larry Desjardin
46 comments
I'm a big proponent of engineers learning financial basics. Why? Because engineers are making decisions all the time, in multiple ways. Having a good financial understanding guides these ...

Flash Poll
Top Comments of the Week
Like Us on Facebook
EE Times on Twitter
EE Times Twitter Feed

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)