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Max The Magnificent
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Re: how many gates?
Max The Magnificent   12/6/2013 12:48:34 PM
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@DrFPGA: ...we know you never exagerate...

I've told you a million times that I don't exagerate LOL. Does anyone still talk about "system gates" -- if so, I can certainly tie all these things together -- I learned all sorts of cool stuff last .... eeek, I can't talk about that yet...

DrFPGA
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Re: how many gates?
DrFPGA   12/6/2013 12:44:24 PM
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I guess this means you are going to finally provide the correct conversion from gates to system gates to 4 input LUTs, etc? All will be revealed is a big promise Max, and we know you never exagerate...

sgabriel
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Re: how many gates?
sgabriel   12/3/2013 8:13:47 PM
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@krisi, that comes out to be >5 billion CMOS transistors in Arria 10. Very impressive for mid-range FPGA, to say the least.

krisi
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Re: how many gates?
krisi   12/3/2013 7:32:05 PM
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thank you @sgabriel...over 1M logic elements, impressive...how many CMOS transistor is that?

sgabriel
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Re: how many gates?
sgabriel   12/3/2013 7:03:38 PM
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@krisi, Altera has disclosed product details of our 20nm Arria 10 family. The largest Arria 10 device has up to 1.15M logic elements, integrated into a mid-range device. And public software support is available today. http://www.altera.com/devices/fpga/arria-fpgas/arria10/arr10-index.jsp

Max The Magnificent
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Re: how many gates?
Max The Magnificent   12/3/2013 3:51:44 PM
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@Kris: ...sounds mysterious Max...

Just call me "Max, Man of Mystery" LOL

krisi
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Re: how many gates?
krisi   12/3/2013 3:42:50 PM
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sounds mysterious Max...looking forward

Max The Magnificent
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Re: how many gates?
Max The Magnificent   12/3/2013 3:34:23 PM
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@Kris: How many gates Xilinx can pack in 20nm process?

I know, but I'm not allowed to tell you just at the moment. All I can say is to keep on visiting Programmable Logic Designline because all will soon be revealed...

krisi
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how many gates?
krisi   12/2/2013 4:27:23 PM
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How many gates Xilinx can pack in 20nm process? Kris



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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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