The cost aspects of Samsung/Toshiba's vertical channel 3D NAND approaches were published last month in the IEEE Transactions on Semiconductor Manufacturing (see the following link for free download: http://bit.ly/1imVpBb)
A description of these cost challenges along with other technical issues can be found here at 3DIncites: http://bit.ly/17c1DPw
The main points are:
(1) If those vertical holes and slits are beyond a few tenths of a degree from the normal (in other words, if they are slightly slanted), the whole concept is no longer economically viable and can be undercut in cost by other approaches.
(2) The string currents rapidly decline as densities/capacities increase to the point where the question arises whether such approaches are indeed foundations for several generations to come or are simply one-offs.
Full disclosure - Both the IEEE paper and the 3DIncites piece were written by me.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.