Also with regards to FPGAs, another test is to drive as many gates as possible all at once for testing power integrity on a board. That causes the FPGA to draw maximum current so you can see what it does to the power rails due to inductance in the power delivery network. Too deep a dive in power can cause havoc and you probably need better or more bypass capacitors on the board.
When performing an emissions test, you usually want worst case and thus many systems have diagnostic software for the purpose of emissions testing. It would be like exercising more FPGA gates than are used in normal operation. Or you might drive a a whole lot of gates at once for a worst-case condition.
Display's also radiate -- CRT's were kind of bad with the magnetic deflection, and the new LCD, etc displays scan the array to update it -- this means that there are effectively long rows of horizontal and vertical ITO traces being switched on and off to make each pixel light or dark -- and ITO must be placed over the whole array to reduce these emmisions -- DO-160 is often hard to pass, for a display designed only to pass FCC/CE
>Of course, there are cable grounding and shielding issues. The most significant is to make a 360° connection with a shield around a connector.
And make the shield connection to the chassis, not digital ground. I once had to clean up a horrendous mess where the designer connected coaxial cable shields to his pcb digital ground plane and could not understand why the radiated emissions were so strong.
A Book For All Reasons Bernard Cole1 Comment Robert Oshana's recent book "Software Engineering for Embedded Systems (Newnes/Elsevier)," written and edited with Mark Kraeling, is a 'book for all reasons.' At almost 1,200 pages, it ...