Remember when we had to do many of the FPGA tricks by hand? Register retiming, one hot state machines, if then else to mux conversions? Now the synthesis tools do all this for us. Hopefully tricks like the multiply by a constant will get folded in too. Just depends on how common the need is for these tricks I guess.
Maybe there should be a 'list' of tricks that users suggest would be good to put into synthesis tools. Perhaps via a discussion thread on Programmable Logic Design Line?
I remember the first time I synthesized an FPGA design for a real product. The synthesizer automatically came up with a one-hot state machine coding. Everything simulated fine. Unfortunately, this particular design did not have a well-formed clock when connecting or disconnecting the input signal, which would cause it to lose the one-hot code occasionally when reconnecting. Switching to a manual state coding that automatically recovered from bad states fixed the problem -- and saved logic cells in this case.
Lesson 1: Don't trust automatic state assignment. Some synthesizers make it hard to turn off automatic state assignment, but it's worth the effort.
Lesson 2: Don't trust simulation. It only simulates theoretical models, not the real world.
Lessons 1+2 combined and generalized: Know the limitations of your tools.
Very important point and one difficult to do in practice. How many tools actually document (in detail) what the tool will do or not do. I find I need to do small example designs and look over th output of the place and route tool to figure out what is going on. Widh the vendors did this for me!
Anyone else have tools with detailed enough docs that they can tell ahead of time what is being done?