Ron, I would expect a crystalline nucleus would yield a fast-crystallizing tail in the retention distribution, which is never seen in our experiments. Rather, the crystallization time shows a normal distribution and no tails, suggesting that crystallization is controlled by the intrinsic properties of the amorphous volume such as composition/structure fluctuations at the few-atom scale. As for the element separation with cycling, it might well contribute to determine the cell endurance. However, we covered 1E5 cycles in our work (Fig. 21) withouth any obvious degradation - actually the distribution slightly improved with cycling. I would conclude the separation is negligible at least in this cycle range.
Daniele "Erratic" and PCM thank you for your clarification with respect to your and my own use of "erratic". I guess in a way I was conditioned by trying to understand PCM related events outside of IEDM. That is the reason for the removal of the 1Gbit PCM-MCP from the products list on Micron's web site, followed more recently (Dec 2013) by the removal of the smaller bit density serial PCM 128Mbit products. Plus the relegation of PCM by Micron from available product status to "promising memory technology" status; with yet another new PCM process now under development. Micron also state on their website "PCM is one of several emerging memory technologies that Micron is investing in".
In relation to crystallization I would also like to clarify a point with respect to my diagram. I showed the case for threshold voltage as a function of volume fraction of crystallites. That is the case where percolation effects come into play and there is a discontinuity in Vt when the first nano-bridge of crystallites links the two electrodes. For the SET situation where there is a large crystal nucleating site already available on which further crystal growth occurs during SET then the Vt = f(VolFrac) curve would I think have a more gentle slope. I discussed the common case where one the electrode is the large nucleating site earlier article in EETimes on data retention and the impact of crystal electrodes.
Daniele- In that case I would think the statistical variation in crystal growth that you mention would depend more on the morphology of the surface of the crystal nucleus after the previous reset operation. I would certainly be interested in your observations on that point and how any element separation with write/erase lifetime would effect the conclusion you draw in your paper.
Thanks for the overview. You have probably been misled by the word *erratic* in Paper 21.7, which you have quoted as an evidence of possible reliability issues affecting PCM technology. I am one of the authors of this work, which clearly states that there are no reliability concerns raised by erratic retention. Erratic retention in this work means that the crystallization time of a PCM cell changes randomly from cycle to cycle, within a narrow time range around the average time to failure. Erratic retention has no impact on the overall retention characteristic of the PCM array: for every cell showing faster crystallization in one cycle, there is another one showing slower crystallization and there are no single bits standing out of the array distribution. Most important, all experiments in the work have been carried out at high temperature, much higher than the typical operation of NVM, to collect data in a reasonable timeframe. Erratic retention, that can be detected only in a time-temperature transition range between consistent retention and consistent data loss, appears at longer times and/or higher temperatures than the product retention specifications. For any further discussion on the erratic retention phenomenon, please refer to our paper in the IEDM proceedings. I will be glad to answer any question.
Resistion-I had CbRAM in the original but I thought I better cover the material options of all the companies with which Micron has joint devopment ventures. You are right, representatives of Sony as co-authors would certainly seem to point in the CbRAM direction. Gives us NV-memory watchers something to look forward to in the new year.
I wish we could get similar summaries on key topics at conferences like this one on the EE Times site. What a benefit this would be to the community. Perhaps an outreach to possible bloggers who could each 'own' a conference and/or topic is called for.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.