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igodard
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Re: Cache Size?
igodard   12/9/2013 5:55:07 PM
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Cache sizes are largely driven by working set of the apps that are running, and those are a mix of the persistent apps (including the OS) and and the temporary needs of the transienyts, including all the "wake me up to check if there's a new version to download" code.

A faster processor is done with the transients sooner, and so the contribution to average working set from the transients is smaller on a Mill. The contribution from the persistent code is relatively fixed, so the working set demand is not reduced that much.

The Mill does reduce the demand for DRAM bandwidth. The reduction varies by application, but 25% is a reasonable rule of thumb - see ootbcomp.com/docs/memory for an explanation. You could reduce the cache sizes, leading to more churn in the cache (and more bandwidth demand) until you were back at the bandwidth of a conventional architecture but a smaller cache. Whether that design point would be worthwhile is very market dependent.

 

Ivan

DrFPGA
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Cache Size?
DrFPGA   12/9/2013 2:46:57 PM
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Seems like there could be a significant advantage in cache size (reduction) vs. traditional architectures. Is that correct? Cache takes up such a big chunk of current CPU designs...



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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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