Can you wrap your brain around the concept of an FPGA containing sufficient programmable fabric to represent the equivalent of 50 million ASIC gates? I knwo I'm struggling with it -- and this number doesn't include and hard IP cores like the transceivers and block RAMs.
@DrFPGA: So in 10 years or so will each of the logic cells in an FPGA also have a different IP (or the IoT equivalent) address?
I'm scared to think -- if you look at th estate of FPGA technology 10 years ago, it was pretty darned impressive, but nothing like what we have today, and back then I woudl never have guessed how far we would have progressed by now .... goodness only knows what will happen in the next 10 years...
i consider these devices so complex, in set up time, to get a working system to market, that i will need perhaps a team of twenty people, just in this expertise alone, , there may be a product in RF, analysis, that can wait out a development of 18 months. but i am sure not most. Perhaps i can be pointed to a design team, that will handle all of this, for a fee, and keep my designs safe from copying. the word boggle, really is put to good use here, i will be going to DesignCon, in San Jose, and will be looking forward to visiting the vendors . When i got 12,000 gates, working at a GigaHertz, i thought , i had acomplished something. but now, i feel like an infant again, perhaps were all zero 'ed out to starting fresh. , i looked at the vendor 's tools, kit boards, the price is not for the faint of heart. you could loose your life in this stuff, but haven't most of us reading this, done so. this is so glue, for a master CPU, or GPU, if you set out to do it. , Cheers all , from Thomas GX, in Vancouver Canada, keep your boards clean and your circuts stright, see you all in San Jose, end of Jan.