"In the future they may not be able to charge the premiumjs for 28nm, 16nm they charge today, but then they will not have the enormous expenditures of new multibillion dollar fabs every 18 monthys either. The biz dynamics will shift radically.
Imagine what that might be like!"
Yes - what egalitarian dreams! I can only imagine the large swaths of un-washed masses storming the bastile. Cake (FinFet) for everyone!
I just spoke with a technologist at a leading OEM and server design company who says Moore's Law ended about ten years and claims to have predicted the end about twelve years ago...whether or not that's true, it seems everyone is finally accepting that the days of packing more transistors and getting a denser and denser product are nearing an end--albeit slowly....
as the R&D cost incurred by the leading Foundry to keep up with Intel shoots up, that cost is bound to get xferred to their Fabless customers, cutting into their huge margin up to now. this is what I had meant as "the free lunch is over for the fabless wonders"
Yes, it is clear thar cost per transistor is not going down with dimension scaling, but new type of scaling - monolithic 3D - would keep Moore's Law in the near future. Samsung is already doing so with 3D NAND and other are moving toward monolithic 3D just as well. The first adaption of monolithic 3D is in the memory segment, and other segment will follow, as we just recently learned whith Qualcomm sign up with CEA Leti. In a recent Blog we articulated why Scaling makes monolithic 3D IC practical http://electroiq.com/blog/2013/10/scaling-makes-monolithic-3d-ic-practical/, and in our site we present the cost and othe benifits the monolithic 3d technology provides - http://www.monolithic3d.com/3d-ic-edge1.html
@Tarra: Fabs like TSMC are just starting to ramp up really expensive (profitable) 3-D stacking processes.
In the future they may not be able to charge the premiumjs for 28nm, 16nm they charge today, but then they will not have the enormous expenditures of new multibillion dollar fabs every 18 monthys either. The biz dynamics will shift radically.
This does level the playing field a bit. Design innovation is where companies will have to distinguish themselves. The best, most efficient design shall survive rather than the design on the latest process node.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.