It actually makes a fair amount of sense that a chip design company could benefit from the end of the era of packing as many transistors as possible onto the chip, given that that necessarily means more innovation in other areas are chip design. Of course, he has an interest in saying that Broadcomm is going to come out on top of the situation regardless.
This does level the playing field a bit. Design innovation is where companies will have to distinguish themselves. The best, most efficient design shall survive rather than the design on the latest process node.
@Tarra: Fabs like TSMC are just starting to ramp up really expensive (profitable) 3-D stacking processes.
In the future they may not be able to charge the premiumjs for 28nm, 16nm they charge today, but then they will not have the enormous expenditures of new multibillion dollar fabs every 18 monthys either. The biz dynamics will shift radically.
Yes, it is clear thar cost per transistor is not going down with dimension scaling, but new type of scaling - monolithic 3D - would keep Moore's Law in the near future. Samsung is already doing so with 3D NAND and other are moving toward monolithic 3D just as well. The first adaption of monolithic 3D is in the memory segment, and other segment will follow, as we just recently learned whith Qualcomm sign up with CEA Leti. In a recent Blog we articulated why Scaling makes monolithic 3D IC practical http://electroiq.com/blog/2013/10/scaling-makes-monolithic-3d-ic-practical/, and in our site we present the cost and othe benifits the monolithic 3d technology provides - http://www.monolithic3d.com/3d-ic-edge1.html
as the R&D cost incurred by the leading Foundry to keep up with Intel shoots up, that cost is bound to get xferred to their Fabless customers, cutting into their huge margin up to now. this is what I had meant as "the free lunch is over for the fabless wonders"