These steps are all good, but there are some crucial steps missing, including these, many of which should come BEFORE you consider others:
A. Floor-planning: Position all high dv/dt components and traces as far away from conductors and connectors that lead to the outside world as possible. In some cases, it even matters which side of an X or Y capacitor, for example, is oriented toward the mains connector, common-mode EMI filter, or other mains-connected device.
B. Floor-planning: In addition to minimizing the area of all high di/dt current loops, route conductors of such loops at right angles relative to possible 'victim' circuit loops.
C. Consider how sizeable current loops can exist in large geometry components. For example, TO247 power transistors can have significant loop area in the Source Drain current loop. Large inductors such as PFC chokes often have an 'equivalent turn' around the core if the windings are not designed to neutralize it, etc.
D. Wherever there is large dv/dt, significant currents WILL flow in parasitic capacitances. This includes transformer primary-secondary capacitances and switching element to heatsink capacitances. Nearby shields intended to prevent radiated EMI can actually make things worse if the loops formed by parasitic capacitances to those shields have sufficient area. For these reasons, put shields close to victim circuits but far from high dv/dt nodes, UNLESS you have a means of connecting the shields in such a way that the loops are small.
E. If there is a relatively long path over which parasitic currents can flow, establish a short path, to minimize loop area. The classic example is "switch-heatsink-victim node". Power transistors and rectifiers usually have significant capacitances to their heatsinks, which, in turn, have large areas and high parasitic capacitance to surrounding conductors. In extreme cases, it may be necessary to interpose a shield between the switching element and the heatsink. Short of that, consider a thick insulator, grounding the heatsink, improving efficiency so that a heatsink is unnecessary, etc.
the list goes on... it all comes down to these principals:
* all currents flow in loops, which should be made as small in area as possible
* I = C * dv/dt, so high dv/dt can cause high current, even if capacitance is small, e.g., parasitic
* V = L * di/dt, so high di/dt can cause high voltage, even if inductances, including mutual inductance, are small
Years ago I asked my Uncle Jim (Ham radio expert @ W2UEN),what was the best way to deal with noisy signals.He said the best way is to stop them at their source.But that's not always possible. Thanks for this timely article EETimes! Skip J. in Titusville,Fl.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.