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Charlie Cheng
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Re: IC industry, the deck is stacked against "start ups"
Charlie Cheng   1/7/2014 7:59:37 PM
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Happy New Year! Sorry it's taken me so long to respond.... 

Sparse matrix is set of linear equations that have little in ways of value for most variables.  I found it interesting at school that techniques to solve them is quite different from ones w/ densely populated variables.  Not that I was any good at Math, but I thought the current business dilmma is strikingly similar to this math problem. 

The trend has indeed been there, probably since before I joined the semiconductor fratnerity.  But it's gotten a LOT worse, because of the skewed scale and the race to super-efficiency.  

Embarrassingly, even if my proposed way to view the problem is correct, I am afraid I don't have a silver bullet to solve this problem.  But trust me, I am trying :-)

Thanks for everyone comments.  Now that I've blogged one, I will blog more, LoL 

tektonikshift
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IC industry, the deck is stacked against "start ups"
tektonikshift   1/2/2014 7:04:55 PM
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Charlie, 

Good article. This trend (increasing complexity, capital, cycle time) has been in place for years. 

"   you would also agree that the odds are more against startups than large semiconductor companies. "

USA based start up IC companies are rare. 

-Tek

HerbR0
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Re: Sparse Matrix
HerbR0   12/30/2013 5:14:28 PM
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Hi, Good questions, thanks!

The best definition of Sparse (and the opposite, Dense) Matrix I found in Wikipedia is at http://en.wikipedia.org/wiki/Sparse_matrix

I can't answer for Charlie and his reasons to express this SoC challenge with MATH terminology. I am sure Charlie will get back to you after the holidays.

I worked for Synopys in the early days of Soc IP adoption. At that time the IDMs and foundries used ONE flavor of process technology for every node and offered high-speed and low-power libraries to add some flexibility for DIGITAL only designs.

For today's mixed signal SoC designs we can't live with such limited "flexibility" any more, so foundries offer - at today's mainstream nodes - process flavors that offer more digital and also mixed-signal design flexibilty BUT complicate IP selection for IC designers. That's the topic Charlie addresses in his blog.

You may have heard already that 16/14 nm processes will become available in only one or very few flavors. You may think the IP selection challenges may go away again. Sorry, not likely --- because these advanced nodes will limit designers' ability to implement very high-speed AND very low-power logic, large memories, analog/RF, etc in the SoC. They'll encourage partitioning into multiple die. This die-level IP, when available, can be mounted side-by-side on an interposer or stacked vertically in one package. The SoC designer can of course, if performance requirements, board-space and power budget allow, also opt for separately packaged functions and assemble these ICs on a PCB.

If you know of a more elegant solution, please share it with us !


Happy New Year ...Herb

 

 

sranje
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Re: Sparse Matrix
sranje   12/30/2013 3:56:45 PM
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Can you please define "sparse matrix"

Why introducing such term?

Is there not an elegant well known alternative?

Perhaps the insights provided are good -- if one would know for certain what are you trying to say and talk about

 

Cheers and Happy 2014 !!

HerbR0
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Re: Sparse Matrix
HerbR0   12/24/2013 2:44:50 PM
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Charlie, Thank you very much for pointing out so clearly a major weakness of our current semiconductor IP offering - too few flavors to give SoC designers full flexibilty in choosing the right process technology for their SoC design.

As you would expect from me, let's use this opportunity to highlight a major benefit of 2.5D and 3D-ICs: HETEROGENEOUS INTEGRATION. As 2.5/3D technologies evolve, system- and IC designers will soon be able to combine their SoC with DIE-LEVEL IP offering different functions (Logic, Memory, Analog, R/F, MEMS,..), manufactured in their most suitable process technology, side-by-side on an interposer or, eventually,even vertically stacked in one package.

Yes, there is still a lot of work ahead of us, to build a strong die-level IP ecosystem and offer true modularity for SoC design.
It's up to System- and IC designers to ask for this Heterogeneous Integration capability and accelerate the necessary development efforts at IP providers.

By the way, "qualifying" proven die-level IP in conjunction with a unique SoC will be much easier and faster than qualifying a soft-IP core together with custom logic.

Looking forward to your comments!...Herb

 

 

junko.yoshida
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Sparse Matrix
junko.yoshida   12/23/2013 5:58:47 PM
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@Charlie, an interesting blog you contributed here. Thank you! However, i am still not sure what exactly you mean by "Sparse Matrix."

Since when has the matrix become "sparse" (wasn't it always sparse?), and what made it "sparse" (Internet?)?

I would appreciate it if you could articulate what you mean by "sparse matrix"....



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