Is multiply by 1000 done with 1000 additions and divide by 1000 done with 1000 subtractions?

Well, no. I was kind of waving my hands and glossing over dirty details. Certainly one way to do it is to do repeated additions or subtractoins (you can do division via addition, as well). When you get down into the guts of the computing machinery, though, we can go about this in different ways - look at the way we do these operations by hand, and we can do things similarly in the computer.

In BCD it's a little harder, but we can do the following type of thing, where each digit has its own combinational cloud to do the multiplication:

123
x 456
=====
738 (this is 123 x 6)
615 (this is 123 x 5, shifted one position to the left)
492 (this is 123 x 4, shifted two positions to the left)
=====
56088

So let's talk about pure binary as an example. For multiplication, you can actually synthesize a 2N-bit combinational cloud to do your multiplications. Lacking that, you can build a state machine that's pretty easy, as binary is a special case. From the same Wikipedia page:

1011 (this is 11 in decimal)
x 1110 (this is 14 in decimal)
======
0000 (this is 1011 x 0)
1011 (this is 1011 x 2, shifted one position to the left)
1011 (this is 1011 x 4, shifted two positions to the left)
+ 1011 (this is 1011 x 8, shifted three positions to the left)
=========
10011010 (this is 154 in decimal)

So, you can see we can do a multiply in (potentially) a lot less operations than just adding them all up.

I mentioned combinationall clouds, so let's touch on that a bit. For all possible N-bit multiplications, a truth table can be made, and a set of discrete logic implemented to perform that multiplication. I will point you to this paper for a quick overview - they show how to implement a 4-bit combinational multiplier and its complexity. The modern synthesis tools appear to be able to create a multiplier of at least 32 bits with no issue (I've not tried anything bigger), and modern FPGAs have dedicated multiplier circuits in them (or so it would seem), but I don't know how many bits wide they are.

I primarily hope to not prove the old addage about letting people think yu a fool, vice opening your mouth and proving you're one... But then, I freely admit that I am, indeed, an idiot, so just keep that in mind, okay?

@Tomii: ALTERA has 9 bit multipliers and 32 bits takes 4 when synthesized. hamster on APP wrote about sign extension for negative numbers also.

This is for 32 bit binary. Recently they have done a lot with floating point, but I did not follow up.

I don't think decimal instructions are available in any RISC. In fact floating point often requires an optional co processor and there is a sign, exponent, mantissa to deal with.

The whole thing is such a mess that converting to hex and formatting output seems easier. Yeah, you need a computer, compiler, etc.

I think there is a typo in the article on its 2nd page - instead of "Taking the nine's complement of 5,940 gives .." I think there should be "Taking the 109's complement of 5,940 gives..."

The nine's complement of 5940 gives 4059, to get ten's complement we need to add 1, which finally gives 4060. Also the difference to the first computation 4337 - 277 is that we need to add the +1 to the result (use 109's complement) because the result is negative.

BCD uses 4 bits, and has 6 "bad" codes for 10 "good" codes: an overhead of 60%. Have you heard of BCK?

Binary Coded Kilo: uses 10 bits, has 24 "bad" codes for 1000 "good" or 2.4% overhead. That equates to 2 bits saved in the code.

The version I saw was in a DDS [Numerically Controlled Oscillator]. 32 bits make 4,000,000,000 instead of 4,294,967,296. So a 200MHz oscillator gave a frequency strep of precisely 0.05 Hz instead of 0.046566128731 Hz [ie. subject to oscillator drift, not rounding error]

Hi, Tom: Things are too quiet here. Altera has 9 bit multipliers and it takes 4 to do 32 bits.

The concerns about precision seem seem exaggerated even in financial calculations. There are rounding methods such that insignifican amounts are discarded.

Given all the complexity of floating point HW, Why not convert the decimal to Hex/Binary and do the algorithm as if doing decimal with pencil and paper then output the whole number part and fractional part converted from binary to decimal?

Too bad this site has no capability to attach anything technical.

The concerns about precision seem seem exaggerated even in financial calculations. There are rounding methods such that insignifican amounts are discarded.

I've seen the repeated additions and other mathematical operations rapidly create some ugly mistakes. I once had a CS class that focused specifically on this, and ways to work within the constraints of the hardware to overcome these errors. It can take a fair amount of massaging!

double dz = 56.75 * 2.3; // 130.5249999999998 int dx = 5675, dy = 23; int dw = 5675 * 23 / 1000; // 130 ,,, 3 decimal points int ddy = dx * dy % 1000; // 525 ,,, compiler rounded up int ddyy = dx * dy % 1000000; // 130525 ( too many zeroes)

Just as on paper, ignore thr decimal point but count decimal points to choose the divisor, divide gets integer quotient and modulo gets numerator of the fraction.

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