Resistion- If, by not practical, you mean that it is not possible to fabricate such a structure then you might be right. Although not included in my review above, I looked at the practicality of the problem of the cumulative thickness of layers building up on the side walls of the vertical structure. Although the devices in the paper are relatively large I did considered a device where the minimum feature size (F) was 20nm, still much larger than where next generation NV memory must go. I also assumed it would be possible to reduce the side wall layer thickness for the TiO,and TaOx to 10nm and I did not leave a centre space; that is I completely filled in the space between the two facing sidewalls of TaOx with tantalum. For a two cell structure this would give a single cell size of a little over 5/2F2, compared with the 4F2 for a simple 2D crossover matrix. The practicality of the repeatable deposition of 10nm films (about 70 atoms thick) on the vertical side walls and then in-filling a deep, high aspect ratio, 10nm wide space between two TaOx surfaces with tantalum is non trivial but in a gedankenexperiment anything is possible.
Resistion: The authors of the 3D Vertical TaOx/TiO2 RRAM paper in their list of claims for their devices stated "forming free, self rectifying, self compliance and highly stable BRS."
I did not investigate the details of the compliance claims any further because I assumed that for some time ahead the array would be monolithically integrated with silicon and the memory array driver/decoder circuits would take care of providing compliance.
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