@mpk.nyy1: the "EASY" botton. becasue after the schematic is complete, you "push" the "autoplace" - "auto-route" button and its DONE, right!!
I once had a digital video camera with enough controls to fly an aircraft -- the best one was actually called "The Easy Button" -- when you pressed that, it turned all of the other controlls off and did everything automatically ... I LOVED that button :-)
Hi Max, I must say I've never had the opportunity to work for a company that could afford all of those nice add-ons and it was only recently I got a hold of Altium for some of those features. About 15 years ago I did a PCI 3 channel image acquisition card with co processor and 2 FPGA's got rev 1 to work without any issues. The biggest challenge was to get 12bit resolution at 1V signal with all of the digital stuff going on. The FPGA code was done with a text editor and Excel and the mechanical dimensioning match up to a daughter board was done with Excel and a vernier. I guess what I'm saying is that apart from using bishop graphics tape (which I've done also) the essentials for 98% of all PCB design tasks really are just schematic and layout. I use the verification part of Altium maybe every 10th design and the FPGA compiler 20th so really I think most of the features aren't used for most designs. Take the wiring loom features you mentioned, great stuff to have but I've never used it because no one had the money to buy it and the thermal simulation I've only ever had a calculator (or excel) and my designs don't overheat because I stick to a bunch of impirical rules on how much power is allowed into how many square millimetres of PCB space without assistance for removal. Yep you won't get a design that is right on the physical limits of what is possible but you'll uually have a more robust design that still works when unobtainium is unavailable. I don't consider myself a brilliant designer just one that loves rule of thumb influenced by 40 years of doing stuff. Per someone elses comment here, let's hope the young guys always have access to those guys who always seems to have an answer to all those questions.
A engineeer knowledgeable in all the implied areas these tools involve!
It seems most engineers know some of these areas.. but most don't know ALL of the areas (electronics , physics, mechanical, manufacturing, business, electrical standards, international standards, documentation standards, etc....
We are doing good to label an electronics engineer as: digital, analog, RF
IF these conditions are met:
- All the BEST tools (features) are available from a single source
- This (mythical) single source will always be the best source for ALL of these tools.
- plus a few additional features (as mentioned by others here)
You MIGHT be able to have a tool set that can be operated by A engineer.
Assuming the supplier does a great job of creating a uniform user interface for all these tools.
(I don't think this is goiing to happen, technology changes too quickly)
What is likely to happen:
- We will continue to use multiple vendors for our tools (competition.. it can be a "good" thing")
- There will be too many interfaces for a single person to be stay knowledgeable and productive with. Both equating to a team requirement for nearly any level of comlexity. This is NOT a good thing.
- and still no common data set for a design that can truly cover ALL the aspects of this large list of tools requires.
We can't even get past the use of gerber file format.
I think a new perspective is needed... and some new standards.
Schematics , HDML, etc.. all have serious limiations in describing a pcb design.
Best cholce: quality people , with tools integrated with their processes.
In a perfect world the clock would be rectangular and if the clock line is routed the same way as the data the clock fronts would be located where the data is stable. So the first orientation would be to keep all the traces equal. On the other hand in the real world data might take a little time to become stable _after_ it was switched from 0 to 1 (or vice versa) and it will also remain stable a little bit after it has started to change. So the middle of the window would be displaced a bit "behind" the halftime. So you could make the clock trace a little slower (longer). On the other hand the receiving circuit needs a little time to recognize the clock edge and would capture the data a little later than the edge. So if both data and clock go from 0 to 1 in the same instant what you would latch would normally be the 1. So that would now be an argument to make the clock trace shorter than the data traces. So you end up where you started - keep them equal. I usually routed the clock trace parallel to the data but inserted a place where I could cut it in order to enable a diversion connectable via two 0 Ohm resistors. I never actually needed this delay, but it was a good feeling to have the option. OK, that was only in the realm of about 67MHz, not really fast stuff ...
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.