Have fun at OFC then, used to go to that trade show...and yes, I rememebr John D/Ambrosia starting 100G efforts 10 years ago...I am just curious what is teh state-of-the-art of this technlogy, used to be very power hungry...if anyone else is interested in giving a talk on this topic feel free to ping me...Kris
@krisi, most of those data streams use 66b/64b encoding and some may use 128b/127b. There was a lot of talk about using forward error correction, particularly where these serial buses might carry data-storage protocols. For example, SATA protocols riding on PCI3 GEN 3 physical layer.
100G Started as 1x10G and now is 2x25G. Well, 4x28G because of bit overhead. Most of the talk at DesignCon is per lane rather than aggregate. The major issue with aggregating is channel-to-channel crosstalk. Most of the issues are just simple getting 26G and 32G to run reliably, All kinds of issues come up such as insertion loss, reflections, intersymbol interference, and skew. At these speeds, differential pairs mismatched by even 1mm have skew prodlems.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.