Wow, I missed the Oscilloscope watch teardown at the show. Good slideshow. I think you hit some important stuff at the show. Martin Rowe might want to chime in about some developments in PCI-Express he saw from the show.
100G Started as 1x10G and now is 2x25G. Well, 4x28G because of bit overhead. Most of the talk at DesignCon is per lane rather than aggregate. The major issue with aggregating is channel-to-channel crosstalk. Most of the issues are just simple getting 26G and 32G to run reliably, All kinds of issues come up such as insertion loss, reflections, intersymbol interference, and skew. At these speeds, differential pairs mismatched by even 1mm have skew prodlems.
@krisi, most of those data streams use 66b/64b encoding and some may use 128b/127b. There was a lot of talk about using forward error correction, particularly where these serial buses might carry data-storage protocols. For example, SATA protocols riding on PCI3 GEN 3 physical layer.
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