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Yang Zhiwei
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about reduction of layers, and other
Yang Zhiwei   2/22/2014 3:28:46 AM
Good summary! Just little complement. In my experience, for 1.0mm or smaller pitch BGA pin fanout, the maximum amount of reduction of layers due to blind-via or micro-via actually depends on the order of via though the increase of line space is more. For one order blind-via based on two times-laminate or one order micro-via from HDI, the amount of layer will reduces only only signal layer or a couple layers.

So,the cost-saving only from the reduction of layers usually is not enough to let HDI solution become cost-effictive. To effect of aspect ratio, it leverages as the PCB thickness is more than 3mm or more than 24 layers than 24 with 1.0 or less pitch BGA application.

For other application scenario, as well as double-side mirror layout the BGA such as memory devices to maximizing the space of layout.

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Blind vias
DU00000001   2/6/2014 11:45:00 AM
My own approach to blind vias was driven by another requirement:

we had to get a sensor module sealed from external humidity. As it is, tracks on the top layer do not work too well with an O-ring seal :(

The solution were blind vias - water tight without the additional costs for plugged vias.

Wish we had started with blind vias sooner (4-layer PCB) as it became clear very soon that they give you a lot of space to route on 2 layers not affected. If there is no requirement for full-blown supply/reference layers you can virtually have 2 independent 2-layer boards to route,

Will never again go without.

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Re: REDUCE COST???? Not likely
jhlewis   2/5/2014 3:56:50 PM
Thank you for your response. I agree completely with everything you stated in your response. The article is well written (other than the title), and addresses aspect ratio issues which are a significant issue with high density boards using microvias. The issues surrounding aspect ratio are not adequately addressed or explained in enough detail for the average PCB designer. Thank you for taking the time to respond.



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Re: REDUCE COST???? Not likely
PZHG   2/5/2014 3:49:15 PM
Hey Jeff,

Thanks for the comment! Like the article describes, using blind and buried vias can reduce your layer count and aspect ratio (just to name a few of the benefits), which can have a big cost impact on high layer count TH PCB. For the PCBs with 16- layers, HDI technology is probably not cost-effective, but when PCB layer count reaches 20+ I find that a) using small TH vias is limited by board aspect ratio and b) 1.00mm or bigger pitch BGAs are necessary for proper breakout. This leads to a larger PCB size, and Blind/Micro/Buried vias can play a role in reducing layer count and PCB size.

The cost model for HDI PCB is not as straightforward as TH PCB, as it is closely tied to HDI layer stack design and varies between boards having same layer count but different HDI layer stack. While HDI technology may be the most cost-effective option for a product, you're absolutely correct that the HDI technology itself is more expensive. I suppose a more accurate title would be "Cost-effective Options For High Layer Count TH PCBs That Use Blind, Buried and Micro Vias".

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REDUCE COST???? Not likely
jhlewis   2/5/2014 12:42:20 PM
FACT: Blind and buried via technology will NOT reduce board cost. It simply enables smaller board footprints to be manufactured that cannot otherwise be built using standard thru-hole technology.

As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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